NRF52820-QDAA-R datasheet(41/437 Pages) NORDIC

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Core components

The debug access port (DAP) implements a standard ARM® CoreSight™ serial wire debug port (SW-DP),

which implements the serial wire debug protocol (SWD). SWD is a two-pin serial interface, see SWDCLK

and SWDIO in Debug overview on page 40.

In addition to the default access port in CPU (AHB-AP), the DAP includes a custom control access port

(CTRL-AP). The CTRL-AP is described in more detail in CTRL-AP - Control access port on page 41.

Note:

• The SWDIO line has an internal pull-up resistor.

• The SWDCLK line has an internal pull-down resistor.

4.8.2 CTRL-AP - Control access port

The control access port (CTRL-AP) is a custom access port that enables control of the device when other

access ports in the DAP are disabled by the access port protection.

Access port protection blocks the debugger from read and write access to all CPU registers and memory-

mapped addresses. See the UICR register APPROTECT on page 36 for more information on enabling

access port protection.

Control access port has the following features:

• Soft reset, see Reset on page 57 for more information

• Disabling of access port protection, which is the reason why CTRL-AP allows control of the device even

when all other access ports in the DAP are disabled by the access port protection

Access port protection is disabled by issuing an ERASEALL command via CTRL-AP. This command will erase

the flash, UICR, and RAM.

4.8.2.1 Registers

Offset

Description

RESET

0x000

Soft reset triggered through CTRL-AP

ERASEALL

0x004

Erase all

ERASEALLSTATUS

0x008

Status register for the ERASEALL operation

APPROTECTSTATUS

0x00C

Status register for access port protection

IDR

0x0FC

CTRL-AP identification register, IDR

Table 13: Register overview

4.8.2.1.1 RESET

Address offset: 0x000

Soft reset triggered through CTRL-AP

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access

Field

Value ID

Value

Description

RW RESET

Soft reset triggered through CTRL-AP. See Reset behavior in

POWER chapter for more details.

NoReset

Reset is not active

Reset

Reset is active. Device is held in reset.

4463_156 v1.0

NRF52820-QDAA-R Datasheet(PDF) 41 Page - Nordic Semiconductor

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