NRF52820-QDAA-R datasheet(19/437 Pages) NORDIC

19 / 437 page

Core components

Base address

Peripheral

Instance

Description

0x40027000

USBD

Universal serial bus device

N/A

0x10000000

FICR

Factory information configuration

N/A

0x10001000

UICR

User information configuration

Table 4: Instantiation table

4.3 NVMC — Non-volatile memory controller

The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory

and the UICR (user information configuration registers).

The CONFIG on page 21 is used to enable the NVMC for writing (CONFIG.WEN = Wen) and erasing

(CONFIG.WEN = Een).

The CPU must be halted before initiating a NVMC operation from the debug system.

4.3.1 Writing to flash

When write is enabled, full 32-bit words can be written to word-aligned addresses in flash memory.

As illustrated in Memory on page 15, the flash is divided into multiple pages. The same 32-bit word in

flash memory can only be written n WRITE number of times before a page erase must be performed.

The NVMC is only able to write

0 to bits in flash memory that are erased (set to 1). It cannot rewrite a bit

back to

1. Only full 32-bit words can be written to flash memory using the NVMC interface. To write less

than 32 bits, write the data as a full 32-bit word and set all the bits that should remain unchanged in the

word to

1. The restriction on the number of writes (nWRITE) still applies in this case.

Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.

The time it takes to write a word to flash is specified by tWRITE. The CPU is halted if the CPU executes code

from the flash while the NVMC is writing to the flash.

NVM writing time can be reduced by using READYNEXT. If this status bit is set to

1, code can perform

the next data write to the flash. This write will be buffered and will be taken into account as soon as the

ongoing write operation is completed.

4.3.2 Erasing a page in flash

When erase is enabled, the flash memory can be erased page by page using the ERASEPAGE on page

22.

After erasing a flash page, all bits in the page are set to

1. The time it takes to erase a page is specified

by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the

flash.

See Partial erase of a page in flash on page 20 for information on dividing the page erase time into

shorter chunks.

4.3.3 Writing to user information configuration registers (UICR)

User information configuration registers (UICR) are written in the same way as flash. After UICR has been

written, the new UICR configuration will only take effect after a reset.

UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR on

page 23 or ERASEALL on page 22. The time it takes to write a word to UICR is specified by tWRITE.

The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the UICR.

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