NRF52820-QDAA-R datasheet(244/437 Pages) NORDIC

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Peripherals

Mode

Clock polarity

Clock phase

CPOL

CPHA

SPI_MODE0

0 (Leading)

0 (Active high)

SPI_MODE1

0 (Leading)

1 (Active low)

SPI_MODE2

1 (Trailing)

0 (Active high)

SPI_MODE3

1 (Trailing)

1 (Active low)

Table 71: SPI modes

6.15.1.1 SPI master mode pin configuration

The different signals SCK, MOSI, and MISO associated with the SPI master are mapped to physical pins.

This mapping is according to the configuration specified in the PSEL.SCK, PSEL.MOSI, and PSEL.MISO

registers respectively. If the CONNECT field of a PSEL.xxx register is set to Disconnected, the associated SPI

master signal is not connected to any physical pin. The PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and

their configurations are only used as long as the SPI master is enabled, and retained only as long as the

device is in ON mode. PSEL.SCK, PSEL.MOSI, and PSEL.MISO must only be configured when the SPI master

is disabled.

To secure correct behavior in the SPI, the pins used by the SPI must be configured in the GPIO peripheral

as described in GPIO configuration on page 244 prior to enabling the SPI. The SCK must always be

connected to a pin, and that pin's input buffer must always be connected for the SPI to work. This

configuration must be retained in the GPIO for the selected I/Os as long as the SPI is enabled.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in

unpredictable behavior.

SPI master signal

SPI master pin

Direction

Output value

SCK

As specified in PSEL.SCK

Output

Same as CONFIG.CPOL

MOSI

As specified in PSEL.MOSI

Output

MISO

As specified in PSEL.MISO

Input

Not applicable

Table 72: GPIO configuration

6.15.1.2 Shared resources

The SPI shares registers and other resources with other peripherals that have the same ID as the SPI.

Therefore, the user must disable all peripherals that have the same ID as the SPI before the SPI can be

configured and used.

Disabling a peripheral that has the same ID as the SPI will not reset any of the registers that are shared

with the SPI. It is therefore important to configure all relevant SPI registers explicitly to secure that it

operates correctly.

See the Instantiation table in Instantiation on page 18 for details on peripherals and their IDs.

6.15.1.3 SPI master transaction sequence

An SPI master transaction is started by writing the first byte, which is to be transmitted by the SPI master,

to the TXD register.

Since the transmitter is double buffered, the second byte can be written to the TXD register immediately

after the first one. The SPI master will then send these bytes in the order they are written to the TXD

The SPI master is a synchronous interface, and for every byte that is sent, a different byte will be received

at the same time. This is illustrated in SPI master transaction on page 245. Bytes that are received will

be moved to the RXD register where the CPU can extract them by reading the register. The RXD register is

double buffered in the same way as the TXD register, and a second byte can therefore be received at the

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NRF52820-QDAA-R Datasheet(PDF) 244 Page - Nordic Semiconductor

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