STA323W datasheet(71/77 Pages) STMICROELECTRONICS

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STA323W

User-programmable settings

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8.9

Fault detect recovery (address 0x2B - 0x2C)

FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is active, the

TRISTATE output immediately goes low and is held low for the time period specified by this

constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default

value of 0x000C specifies approximately 0.1 ms.

8.10

Status indicator register (address 0x2D)

STATUS register bits serve the purpose of communicating the detected error or warning

condition to the user. This is a read-only register and writing to this register would not be of

any consequence.

8.10.1

Thermal warning indicator

If the power stage thermal operating conditions are exceeded, the thermal warning indicator

transmits a signal to the digital logic block to initiate a corrective procedure. This register bit

is set to 0 to indicate a thermal warning and it reverts back to its default state as soon as the

cause of the thermal warning has been corrected.

8.10.2

Fault detect indicator

As soon as the power stage issues a Fault error signal, thereby initiating the Fault recovery

procedure described in Section 8.9, this register bit is set to 0 to indicate the error to the

user. As soon as the fault condition (over-current or thermal) is corrected, this bit is reset

back to its default state.

FRDC15

FDRC14

FDRC13

FDRC12

FDRC11

FDRC10

FDRC9

FDRC8

000

FDRC7

FDRC6

FDRC5

FDRC4

FDRC3

FDRC2

FDRC1

FDRC0

110

PLULL

Reserved

FAULT

TWARN

00000

Table 71.

Thermal warning indicator

Bit

R/W

RST

Name

Description

0RO

RWRAN

0: thermal warning detected

1: normal operation (no thermal warning)

Table 72.

Fault detect indicator

Bit

R/W

RST

Name

Description

1RO

FAULT

0: fault issued from the power stage

1: normal operation (no fault)

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