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STA323W Datasheet(PDF) 34 Page - STMicroelectronics

Part # STA323W
Description  2.1-channel high-efficiency digital audio system
PDF  77 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA323W Datasheet(HTML) 34 Page - STMicroelectronics

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I2C bus specification
STA323W
34/77
6.3
Write operation
Figure 44.
I2C write procedure
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA323W acknowledges this and then the master writes the internal address byte.
After receiving the internal byte address the STA323W again responds with an
acknowledgement.
Byte write
In the byte write mode the master sends one data byte. This is acknowledged by the
STA323W. The master then terminates the transfer by generating a STOP condition.
Multi-byte write
The multi-byte write modes can start from any internal address. Sequential data bytes are
written to sequential addresses within the STA323W.
The master generates a STOP condition to terminate the transfer.
6.4
Read operation
Figure 45.
I2C read procedure
Current address byte read
Following the START condition the master sends a device select code with the RW bit set
to 1. The STA323W acknowledges this and then responds by sending one byte of data. The
master then terminates the transfer by generating a STOP condition.
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DATA IN
ACK
STOP
BYTE
WRITE
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DATA IN
ACK
STOP
MULTIBYTE
WRITE
DATA IN
ACK
DEV-ADDR
ACK
START
RW
DATA
NO ACK
STOP
CURRENT
ADDRESS
READ
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DEV-ADDR
ACK
STOP
RANDOM
ADDRESS
READ
DATA
NO ACK
START
RW
DEV-ADDR
ACK
START
DATA
ACK
DATA
ACK
STOP
SEQUENTIAL
CURRENT
READ
DATA
NO ACK
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DEV-ADDR
ACK
SEQUENTIAL
RANDOM
READ
DATA
ACK
START
RW
DATA
ACK
NO ACK
STOP
DATA
RW=
HIGH



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