DS72011RB120FPV datasheet(357/1196 Pages) RENESAS

357 / 1196 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 329 of 1164

REJ09B0321-0200

Bit

Bit Name

Initial

Value

R/W

Description

23 to 17



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DREQ

R/W

DMA Request

This bit is used to check whether a DMA request is

currently present.

Furthermore, when the software trigger is selected

(DCTG = "000000") by the DMA request source

selection bits (DCTG), DMA requests operate through

this bit.

The value of this bit changes according to the state of

DMA request input to the DMAC regardless of the

settings of the DMAC module activation bit (DMST)

and DMA transfer enable bit (DEN). The conditions for

setting and clearing the bit are determined by the DMA

request source selection bits (DCTG) and input sense

mode selection bits (STRG) as described below.

(a) When software triggering is selected (DCTG =

"000000") by the DMA request source selection

bits (DCTG).

• Condition for setting to "1"

This bit is set to "1" when a "1" is written to it by

software, generating the DMA request.

• Condition for clearing to "0"

This bit is cleared to "0" by either of the below

events.

 Software writing a "0" to the bit

 The start of the transfer operation

corresponding to the bit setting

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