DS72011RB120FPV datasheet(361/1196 Pages) RENESAS

361 / 1196 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 333 of 1164

REJ09B0321-0200

Bit

Bit Name

Initial

Value

R/W

Description

DSCLR

R/W

DMA Internal State Clear

Writing a "1" to this bit stops DMA transfer in the

middle of a sequence of DMA transfer, suspending the

remainder of the transfer and initializing the internal

state of the DMAC. Writing a "1" to this bit only clears

the transfer state of the DMAC internal circuit. The

other registers are not initialized. Writing "0" is invalid

and a "1" written to this bit is not retained. This bit is

always read as "0".

Note: This bit must only be written to when the

corresponding channel is not in the midst of

single operand transfer (DASTS in the channel

corresponding to the DMA arbitration status

been disabled (DMST in the DMA activation

control register (DMSCNT) or DEN in DMA

control register B (DMCNTBn) is set to "0").

Operation is not guaranteed when this bit is

written to while these conditions do not apply.

When reading:

Always read as "0"

When writing:

0: Invalid

1: Initializes the DMAC's internal state

Note:

When the software trigger is selected as the DMA request source, the DMA request bit

(DREQ) can be set to "1" regardless of the settings of the DMA transfer enable bit (DEN)

and DMAC module activation bit (DMST) and whether or not a transfer operation is

currently in progress. However, even if the software trigger is selected as the DMA request

source, only clear the DMA request bit (DREQ) to "0" or write to the DMAC internal state

clearing bit (DSCLR) when a transfer operation is not in process on the corresponding

channel (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is

"0") and DMA transfer has been disabled (DMST in the DMA activation control register

(DMSCNT) or DEN in the DMA control register B (DMCNTBn) is set to "0"). Operation is not

guaranteed if this register is written to when these conditions are not satisfied.

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