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DS72011RB120FPV Datasheet(PDF) 256 Page - Renesas Technology Corp |
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DS72011RB120FPV Datasheet(HTML) 256 Page - Renesas Technology Corp |
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256 / 1196 page ![]() Section 9 Bus State Controller (BSC) Rev. 2.00 Sep. 07, 2007 Page 228 of 1164 REJ09B0321-0200 9.4.11 SDRAM Power-Down Control Register (SDPWDCNT) SDPWDCNT controls transition to and recovery from power-down mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: Initial value: R/W: 15 14 13 12 11 10 9876543210 Bit: Initial value: R/W: 0 000000000000000 R RRRRRRRRRRRRRRR 0 000000000000000 R RRRRRRRRRRRRRR R/W — — — — — — — — — — — — — — — — — — — — — — — — — — — — —— — DPWD Bit Bit Name Initial Value R/W Description 31 to 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 DPWD 0 R/W SDRAM Common Power-Down Enable This bit controls transition to and recovery from power- down mode for all channels simultaneously. Setting DPWD to 1 causes all channels to transition to power- down mode. Clearing DPWD to 0 causes all channels to recover from power-down mode. If an auto-refresh is in progress, the transition to power-down mode is delayed until the auto-refresh completes. 0: Power-down disabled 1: Power-down enabled |
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