R5F72115D160FPV datasheet(716/1228 Pages) RENESAS

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Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 692 of 1200

REJ09B0344-0200

15.3.9

FIFO Control Register (SCFCR)

SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger

data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and

written to by the CPU. It is initialized to H'0000 by a power-on reset.

0000000000000000

R/W

Bit:

Initial value:

R/W:

-----

---

RTRG[1:0]

TTRG[1:0]

TFRST RFRST

LOOP

Bit

Bit Name

Initial

Value

R/W

Description

15 to 8

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

Receive FIFO Data Trigger

Set the quantity of receive data which sets the receive

data full (RDF) flag in the serial status register (SCFSR).

The RDF flag is set to 1 when the quantity of receive

data stored in the receive FIFO register (SCFRDR) is

increased more than the set trigger number shown

below.

• Asynchronous mode • Clocked synchronous mode

7, 6

RTRG[1:0]

R/W

00: 1

01: 4

10: 8

11: 14

00: 1

01: 2

10: 8

11: 14

Note:

In clock synchronous mode, to transfer the

receive data using DMAC, set the receive trigger

number to 1. If set to other than 1, CPU must

read the receive data left in SCFRDR.

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