R5F72115D160FPV datasheet(717/1228 Pages) RENESAS

717 / 1228 page

Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 693 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

5, 4

TTRG[1:0]

R/W

Transmit FIFO Data Trigger

Set the quantity of remaining transmit data which sets

the transmit FIFO data register empty (TDFE) flag in the

serial status register (SCFSR). The TDFE flag is set to 1

when the quantity of transmit data in the transmit FIFO

data register (SCFTDR) becomes less than the set

trigger number shown below.

00: 8 (8)*

01: 4 (12)*

10: 2 (14)*

11: 0 (16)*

Note: * Values in parentheses mean the number of

empty bytes in SCFTDR when the TDFE flag is

set to 1.

—

Reserved

This bit is always read as 0. The write value should

always be 0.

TFRST

R/W

Transmit FIFO Data Register Reset

Disables the transmit data in the transmit FIFO data

0: Reset operation disabled*

1: Reset operation enabled

Note: * Reset operation is executed by a power-on

reset.

RFRST

R/W

Receive FIFO Data Register Reset

Disables the receive data in the receive FIFO data

0: Reset operation disabled*

1: Reset operation enabled

Note: * Reset operation is executed by a power-on

reset.

LOOP

R/W

Loop-Back Test

Internally connects the transmit output pin (TXD) and

receive input pin (RXD) and internally connects the

RTS

pin and

CTS pin and enables loop-back testing.

0: Loop back test disabled

1: Loop back test enabled

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