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H8/3021 Datasheet(PDF) 332 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 332 Page - Renesas Technology Corp |
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332 / 712 page  9. Programmable Timing Pattern Controller Rev.2.00 Mar. 22, 2007 Page 308 of 684 REJ09B0352-0200 Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 9.5 shows an example in which the TPC is used for cyclic five-phase pulse output. GRA H'0000 NDRA PADR TP7 TP6 TP5 TP4 TP3 • • • • Time 80 TCNT TCNT value C0 40 60 20 30 10 18 08 88 80 C0 Compare match The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A. The trigger period is set in GRA. The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt. H'F8 is written in PADDR and NDERA, and bits G1CMS1, G1CMS0, G0CMS1, and G0CMS0 are set in TPCR to select compare match in the ITU channel set up in step 1 as the output trigger. Output data H'80 is written in NDRA. The timer counter in this ITU channel is started. When compare match A occurs, the NDRA contents are transferred to PADR and output. The compare match/input capture A (IMFA) interrupt service routine writes the next output data (H'C0) in NDRA. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive IMFA interrupts. 00 80 C0 40 60 20 30 10 18 08 88 80 C0 40 Figure 9.5 Normal TPC Output Example (Five-Phase Pulse Output) |
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