H8SLASH3021 datasheet(334/712 Pages) RENESAS

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9. Programmable Timing Pattern Controller

Rev.2.00 Mar. 22, 2007 Page 310 of 684

REJ09B0352-0200

Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non-

Overlapping Output): Figure 9.7 shows an example of the use of TPC output for four-phase

complementary non-overlapping pulse output.

GRB

H'0000

NDRA

PADR

TP7

TP6

TP5

TP4

TP3

TP2

TP1

TP0

Time

TCNT

period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable

IMFA interrupts.

H'FF is written in PADDR and NDERA, and bits G1CMS1, G1CMS0, G0CMS1, and G0CMS0 are set in

TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.

TCNT value

Non-overlap margin

The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output

compare registers and the counter will be cleared by compare match B. The TPC output trigger

•

Bits G1NOV and G0NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is

written in NDRA.

The timer counter in this ITU channel is started. When compare match B occurs, outputs change from

1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed

by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRA.

Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95...

at successive IMFA interrupts.

GRA

Figure 9.7 Non-Overlapping TPC Output Example

(Four-Phase Complementary Non-Overlapping Pulse Output)

H8/3021 Datasheet(PDF) 334 Page - Renesas Technology Corp