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H8/3021 Datasheet(PDF) 548 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 548 Page - Renesas Technology Corp |
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548 / 712 page  17. Power-Down State Rev.2.00 Mar. 22, 2007 Page 524 of 684 REJ09B0352-0200 17.7 System Clock Output Disabling Function Output of the system clock ( φ) can be controlled by the PSTOP bit in MSTCR. When the PSTOP bit is set to 1, output of the system clock halts and the φ pin is placed in the high-impedance state. Figure 17.3 shows the timing of the stopping and starting of system clock output. When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 17.4 indicates the state of the φ pin in various operating states. T1 T2 (PSTOP = 1) T3 T1 T2 (PSTOP = 0) MSTCR write cycle MSTCR write cycle High impedance φ pin T3 Figure 17.3 Timing of Starting and Stopping of φ Clock Oscillation Table 17.4 φ Pin State in Various Operating States Operating State PSTOP = 0 PSTOP = 1 Hardware standby High impedance High impedance Software standby Always high High impedance Sleep mode System clock output High impedance Normal operation System clock output High impedance |
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