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H8/3021 Datasheet(PDF) 699 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 699 Page - Renesas Technology Corp |
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699 / 712 page  Appendix D. Pin States Rev.2.00 Mar. 22, 2007 Page 675 of 684 REJ09B0352-0200 D.2 Pin States at Reset Reset in T1 State: Figure D.1 is a timing diagram for the case in which RES goes low during the T1 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The address bus is initialized to the low output level 0.5 state after the low level of RES is sampled. Sampling of RES takes place at the fall of the system clock (φ). Access to external address φ RES H'000000 High impedance High impedance High High High Internal reset signal T1 T2 T3 RD (read access) (modes 1, 3, 5, 6) WR (write access) (modes 1, 3, 5, 6) Data bus (write access) (modes 1, 3, 5, 6) I/O port (modes 1, 3, 5 to 7) Address bus (modes 1, 3, 5, 6) AS (modes 1, 3, 5, 6) Figure D.1 Reset during Memory Access (Reset during T1 State) |
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