H8SLASH3021 datasheet(701/712 Pages) RENESAS

Part #	H8/3021

Description	16-Bit Single-Chip Microcomputer

PDF	712 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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701 / 712 page

Appendix D. Pin States

Rev.2.00 Mar. 22, 2007 Page 677 of 684

REJ09B0352-0200

Reset in T3 State: Figure D.3 is a timing diagram for the case in which

RES goes low during the

3 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to

the input state.

AS, RD, and WR go high, and the data bus goes to the high-impedance state. The

address bus outputs are held during the T

3 state.The same timing applies when a reset occurs in the

2 state of an access cycle to a two-state-access area.

RES

High impedance

Internal

reset signal

Access to external address

H'000000

RD (read access)

(modes 1, 3, 5, 6)

WR (write access)

(modes 1, 3, 5, 6)

Data bus

(write access)

(modes 1, 3, 5, 6)

I/O port

(modes 1, 3, 5 to 7)

Address bus

(modes 1, 3, 5, 6)

AS (modes 1, 3, 5, 6)

Figure D.3 Reset during Memory Access (Reset during T3 State)

H8/3021 Datasheet(PDF) 701 Page - Renesas Technology Corp