H8SLASH3021 datasheet(700/712 Pages) RENESAS

Part #	H8/3021

Description	16-Bit Single-Chip Microcomputer

PDF	712 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Appendix D. Pin States

Rev.2.00 Mar. 22, 2007 Page 676 of 684

REJ09B0352-0200

Reset in T2 State: Figure D.2 is a timing diagram for the case in which

RES goes low during the

T2 state of an external memory access cycle. As soon as

RES goes low, all ports are initialized to

the input state.

AS, RD, and WR go high, and the data bus goes to the high-impedance state. The

address bus is initialized to the low output level 0.5 state after the low level of

RES is sampled.

The same timing applies when a reset occurs during a wait state (T

W).

RES

H'000000

High impedance

Internal

reset signal

Access to external address

RD (read access)

(modes 1, 3, 5, 6)

WR (write access)

(modes 1, 3, 5, 6)

Data bus

(write access)

(modes 1, 3, 5, 6)

I/O port

(modes 1, 3, 5 to 7)

Address bus

(modes 1, 3, 5, 6)

AS (modes 1, 3, 5, 6)

Figure D.2 Reset during Memory Access (Reset during T2 State)

H8/3021 Datasheet(PDF) 700 Page - Renesas Technology Corp