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H8/3021 Datasheet(PDF) 702 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 702 Page - Renesas Technology Corp |
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702 / 712 page  Appendix E. Timing of Transition to and Recovery from Hardware Standby Mode Rev.2.00 Mar. 22, 2007 Page 678 of 684 REJ09B0352-0200 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns). t1 ≥ 10tcyc t2 ≥ 0 ns STBY RES (2) When the RAME bit is cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately 100 ns before STBY goes high. STBY RES t ≥ 100 ns tOSC |
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