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H8/3021 Datasheet(PDF) 249 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 249 Page - Renesas Technology Corp |
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249 / 712 page  8. 16-Bit Integrated Timer Unit (ITU) Rev.2.00 Mar. 22, 2007 Page 225 of 684 REJ09B0352-0200 Internal data bus CPU H L Bus interface H L Module data bus TCNTH TCNTL Figure 8.11 Access to Timer Counter (CPU Reads TCNT, Lower Byte) 8.3.2 8-Bit Accessible Registers The registers other than the timer counters, general registers, and buffer registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus. Figures 8.12 and 8.13 show examples of byte read and write access to a TCR. If a word-size data transfer instruction is executed, two byte transfers are performed. Internal data bus CPU H L Bus interface H L Module data bus TCR Figure 8.12 TCR Access (CPU Writes to TCR) Internal data bus CPU H L Bus interface H L Module data bus TCR Figure 8.13 TCR Access (CPU Reads TCR) |
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