H8SLASH3021 datasheet(250/712 Pages) RENESAS

250 / 712 page

8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 226 of 684

REJ09B0352-0200

8.4

Operation

8.4.1

Overview

A summary of operations in the various modes is given below.

Normal Operation: Each channel has a timer counter and general registers. The timer counter

counts up, and can operate as a free-running counter, periodic counter, or external event counter.

General registers A and B can be used for input capture or output compare.

Synchronous Operation: The timer counters in designated channels are preset synchronously.

Data written to the timer counter in any one of these channels is simultaneously written to the

timer counters in the other channels as well. The timer counters can also be cleared synchronously

if so designated by the CCLR1 and CCLR0 bits in the TCRs.

PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare

match A and to 0 at compare match B. The duty cycle can be varied from 0

% to 100% depending

on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB

automatically become output compare registers.

Reset-Synchronized PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with

complementary waveforms. (The three phases are related by having a common transition point.)

When reset-synchronized PWM mode is selected GRA3, GRB3, GRA4, and GRB4 automatically

function as output compare registers, TIOCA

3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and

TOCXB

4 function as PWM output pins, and TCNT3 operates as an up-counter. TCNT4 operates

independently, and is not compared with GRA4 or GRB4.

Complementary PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with

non-overlapping complementary waveforms. When complementary PWM mode is selected

GRA3, GRB3, GRA4, and GRB4 automatically function as output compare registers, and

TIOCA

3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 function as PWM output pins.

TCNT3 and TCNT4 operate as up/down-counters.

Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and

TCLKB is detected and TCNT2 counts up or down accordingly. When phase counting mode is

selected TCLKA and TCLKB become clock input pins and TCNT2 operates as an up/down-

counter.

H8/3021 Datasheet(PDF) 250 Page - Renesas Technology Corp