H8SLASH3004 datasheet(8/497 Pages) RENESAS

8 / 497 page

2.9

Basic Operational Timing ............................................................................................... 49

2.9.1

Overview......................................................................................................... 49

2.9.2

On-Chip Memory Access Timing................................................................... 49

2.9.3

On-Chip Supporting Module Access Timing ................................................. 51

2.9.4

Access to External Address Space.................................................................. 52

Section 3

MCU Operating Modes........................................................................... 53

3.1

Overview ........................................................................................................................ 53

3.1.1

Operating Mode Selection .............................................................................. 53

3.1.2

3.2

Mode Control Register (MDCR) .................................................................................... 55

3.3

System Control Register (SYSCR)................................................................................. 56

3.4

Operating Mode Descriptions......................................................................................... 58

3.4.1

Mode 1 ............................................................................................................ 58

3.4.2

Mode 3 ............................................................................................................ 58

3.5

Memory Map in Each Operating Mode.......................................................................... 58

Section 4

Exception Handling.................................................................................. 61

4.1

Overview ........................................................................................................................ 61

4.1.1

Exception Handling Types and Priority.......................................................... 61

4.1.2

Exception Handling Operation ....................................................................... 61

4.1.3

Exception Vector Table ................................................................................... 62

4.2

Reset

........................................................................................................................63

4.2.1

Overview......................................................................................................... 63

4.2.2

Reset Sequence ............................................................................................... 63

4.2.3

Interrupts after Reset....................................................................................... 65

4.3

Interrupts ........................................................................................................................ 65

4.4

Trap Instruction............................................................................................................... 66

4.5

Stack Status after Exception Handling ........................................................................... 66

4.6

Notes on Stack Usage ..................................................................................................... 67

Section 5

Interrupt Controller................................................................................... 69

5.1

Overview ........................................................................................................................ 69

5.1.1

Features........................................................................................................... 69

5.1.2

Block Diagram................................................................................................ 70

5.1.3

Pin Configuration............................................................................................ 71

5.1.4

5.2

Register Descriptions...................................................................................................... 72

5.2.1

System Control Register (SYSCR)................................................................. 72

5.2.2

Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 73

5.2.3

IRQ Status Register (ISR) .............................................................................. 79

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