H8SLASH3028 datasheet(67/923 Pages) RENESAS

67 / 923 page

Rev. 2.00, 09/03, page 37 of 890

Table 2.9

System Control Instructions

Instruction

Size*

Function

TRAPA

—

Starts trap-instruction exception handling

RTE

—

Returns from an exception-handling routine

SLEEP

—

Causes a transition to the power-down state

LDC

B/W

(EAs)

→ CCR

Moves the source operand contents to the condition code register. The

condition code register size is one byte, but in transfer from memory, data

is read by word access.

STC

B/W

CCR

→ (EAd)

Transfers the CCR contents to a destination location. The condition code

access.

ANDC

CCR

∧ #IMM → CCR

Logically ANDs the condition code register with immediate data.

ORC

CCR

∨ #IMM → CCR

Logically ORs the condition code register with immediate data.

XORC

CCR

⊕ #IMM → CCR

Logically exclusive-ORs the condition code register with immediate data.

NOP

—

PC + 2

→ PC

Only increments the program counter.

Note: * Size refers to the operand size.

B: Byte

W: Word

Table 2.10 Block Transfer Instruction

Instruction

Size

Function

EEPMOV.B

—

if R4L

≠ 0 then

repeat

@ER5+

→ @ER6+, R4L – 1 → R4L

until

R4L = 0

else next;

EEPMOV.W

—

if R4

≠ 0 then

repeat

@ER5+

→ @ER6+, R4 – 1 → R4

until

R4 = 0

else next;

Block transfer instruction. This instruction transfers the number of data

bytes specified by R4L or R4, starting from the address indicated by ER5,

to the location starting at the address indicated by ER6. At the end of the

transfer, the next instruction is executed.

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