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H8/3028 Datasheet(PDF) 7 Page - Renesas Technology Corp |
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H8/3028 Datasheet(HTML) 7 Page - Renesas Technology Corp |
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7 / 923 page  Rev. 2.00, 09/03, page vii of xxx Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) 1.2 Block Diagram Figure 1.1 Block Diagram 6 Figure amended MD MD MD EXTAL XTAL STBY RES NMI 2 1 0 Interrupt controller φ/P67 LWR/P66 HWR/P65 RD/P64 AS/P63 BACK/P62 BREQ/P61 WAIT/P60 RESO/FWE* ROM (mask ROM or flash memory) 9 Table amended System control RES 63 Input Reset input: When driven low, this pin resets the chip 1.3.2 Pin Functions Table 1.2 Pin Functions RESO 10 Output Reset output (mask ROM version): Outputs the reset signal generated by the watchdog timer to an external device FWE 10 Input Write enable signal (F-ZTAT version): Flash memory write control signal 7.4.8 DMAC Bus Cycle Figure 7.13 DMA Transfer Bus Timing (Example) 229 Figure amended φ RD HWR LWR T1 T2 T1 T2 Td T1 T2 T1 T2 T3 T1 T2 T3 T1 T2 T1 T2 CPU cycle DMAC cycle (1 word transfer) CPU cycle Source address Destination address Address bus |
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