H8SLASH3028 datasheet(106/923 Pages) RENESAS

106 / 923 page

Rev. 2.00, 09/03, page 76 of 890

4.3

Interrupts

Interrupt exception handling can be requested by seven external sources (NMI, IRQ0 to IRQ5), and

36 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources

and indicates the number of interrupts of each type.

The on-chip supporting modules that can request interrupts are the watchdog timer (WDT),

DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication

interface (SCI), and A/D converter. Each interrupt source has a separate vector address.

NMI is the highest-priority interrupt and is always accepted*. Interrupts are controlled by the

interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority

levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt

priority registers A and B (IPRA and IPRB) in the interrupt controller.

Note: * In the flash memory version, NMI input is sometimes disabled. For details see section

18.9, NMI Input Disable Conditions.

For details on interrupts see section 5, Interrupt Controller.

Interrupts

External interrupts

Internal interrupts

NMI (1)

IRQ to IRQ (6)

WDT*1 (1)

DRAM interface*2 (1)

16-bit timer (9)

8-bit timer (8)

DMAC (4)

SCI (12)

A/D converter (1)

Notes: Numbers in parentheses are the number of interrupt sources.

1. When the watchdog timer is used as an interval timer, it generates an interrupt request

at every counter overflow.

2. When the DRAM interface is used as an interval timer, it generates an interrupt request

at compare match.

Figure 4.5 Interrupt Sources and Number of Interrupts

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