M38K09RFS datasheet(150/328 Pages) RENESAS

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2.2 Interrupt

Rev.2.00

Oct 05, 2006

page 21 of 111

38K0 Group

REJ09B0337-0200

APPLICATION

2.2.8 Notes on interrupts

(1)

Change of relevant register settings

When the setting of the following registers or bits is changed, the interrupt request bit may be set

to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following

sequence.

•Interrupt edge selection register (address 0FF316)

•Timer X mode register (address 2316)

Set the above listed registers or bits as the following sequence.

Fig. 2.2.15 Sequence of changing relevant register

s Reason

When setting the following, the interrupt request bit may be set to “1”.

•When setting external interrupt active edge

Concerned register: Interrupt edge selection register (address 0FF316)

Timer X mode register (address 2316)

Set the corresponding interrupt enable bit to “0”

(disabled) .

↓

Set the interrupt edge select bit (active edge switch

bit) or the interrupt (source) select bit to “1”.

↓

NOP (One or more instructions)

↓

Set the corresponding interrupt request bit to “0”

(no interrupt request issued).

↓

Set the corresponding interrupt enable bit to “1”

(enabled).

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