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M38K09RFS Datasheet(PDF) 148 Page - Renesas Technology Corp |
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M38K09RFS Datasheet(HTML) 148 Page - Renesas Technology Corp |
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148 / 328 page  2.2 Interrupt Rev.2.00 Oct 05, 2006 page 19 of 111 38K0 Group REJ09B0337-0200 APPLICATION 2.2.7 Key input interrupt A key input interrupt request is generated by applying “L” level to any port P0 pin that has been set to the input mode. In other words, it is generated when AND of the input level goes from “1” to “0”. (1) Connection example when Key input interrupt is used When using the Key input interrupt, compose an active-low key matrix which inputs to port P0. Figure 2.2.13 shows a connection example and the port P0 block diagram when using a key input interrupt. In the connection example in Figure 2.2.13, a key input interrupt request is generated by pressing one of the keys corresponding to ports P00 to P03. Fig. 2.2.13 Connection example and port P0 block diagram when using key input interrupt ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ Port P00 latch Port P00 direction register = “0” Port P01 latch Port P01 direction register = “0” Port P02 latch Port P02 direction register = “0” Port P03 latch Port P03 direction register = “0” Port P04 latch Port P04 direction register = “1” Port P05 latch Port P05 direction register = “1” Port P06 latch Port P06 direction register = “1” Port P07 latch Port P07 direction register = “1” P00 input P01 input P02 input P03 input P04 output P05 output P06 output P07 output PULL 0 register Bit 7 = “0” Port P0 Input reading circuit Port PXx “L” level output ✽ P-channel transistor for pull-up ✽ ✽ CMOS output buffer Key input interrupt request PULL 0 register Bit 6 = “0” PULL 0 register Bit 5 = “0” PULL 0 register Bit 4 = “0” PULL 0 register Bit 3 = “1” PULL 0 register Bit 2 = “1” PULL 0 register Bit 1 = “1” PULL 0 register Bit 0 = “1” |
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