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AT89C51ED2-RDTUM Datasheet(PDF) 72 Page - ATMEL Corporation |
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AT89C51ED2-RDTUM Datasheet(HTML) 72 Page - ATMEL Corporation |
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72 / 137 page  72 4235K–8051–05/08 AT89C51RD2/ED2 17. Interrupt System The AT89C51RD2/ED2 has a total of 9 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 17-1. Figure 17-1. Interrupt Control System Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (Table 17-4 and Table 17-6). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 17-7) and in the Interrupt Priority High register (Table 17-5 and Table 17-6) shows the bit values and priority levels associated with each combination. IE1 0 3 High Priority Interrupt Interrupt Polling Sequence, Decreasing from High to Low Priority Low Priority Interrupt Global Disable Individual Enable EXF2 TF2 TI RI TF0 INT0 INT1 TF1 IPH, IPL IE0 0 3 0 3 0 3 0 3 0 3 0 3 PCA IT KBD IT SPI IT 0 3 0 3 |
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