AT89C51ED2-RDTUM datasheet(24/137 Pages) ATMEL

24 / 137 page

4235K–8051–05/08

AT89C51RD2/ED2

part of the available XRAM as explained in Table 9-1. This can be useful if external

peripherals are mapped at addresses already used by the internal XRAM.

• With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in

combination with any of the registers R0, R1 of the selected bank or DPTR. An access to

XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM =

0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H

rather than external memory. An access to external data memory locations higher than the

accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same

way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7

as write and read timing signals. Accesses to XRAM above 0FFH can only be done by the

use of DPTR.

• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard

80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any

output port pins can be used to output higher order address bits. This is to provide the

external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs

the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order

eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read

or write signals on P3.6 (WR) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)

internal data memory. The stack may not be located in the XRAM.

The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are

extended from 6 to 30 clock periods. This is useful to access external slow peripherals.

9.1

Registers

Table 9-1.

AUXR Register

AUXR - Auxiliary Register (8Eh)

DPU

XRS2

XRS1

XRS0

EXTRAM

Bit

Number

Bit

Mnemonic

Description

DPU

Disable Weak Pull-up

Cleared by software to activate the permanent weak pull-up (default)

Set by software to disable the weak pull-up (reduce power consumption)

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Pulse length

Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods

(default).

Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.

XRS2

XRAM Size

XRS2XRS1XRS0XRAM size

0256 bytes

512 bytes

0768 bytes(default)

11024 bytes

01792 bytes

XRS1

XRS0

AT89C51ED2-RDTUM Datasheet(PDF) 24 Page - ATMEL Corporation

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