AT89C51ED2-RDTUM datasheet(74/137 Pages) ATMEL

74 / 137 page

4235K–8051–05/08

AT89C51RD2/ED2

Table 17-3.

IENO Register

IEN0 - Interrupt Enable Register (A8h)

Reset Value = 0000 0000b

Bit addressable

ET2

ET1

EX1

ET0

EX0

Bit

Number

Bit

Mnemonic

Description

Enable All interrupt bit

Cleared to disable all interrupts.

Set to enable all interrupts.

PCA interrupt enable bit

Cleared to disable.

Set to enable.

ET2

Timer 2 overflow interrupt Enable bit

Cleared to disable timer 2 overflow interrupt.

Set to enable timer 2 overflow interrupt.

Serial port Enable bit

Cleared to disable serial port interrupt.

Set to enable serial port interrupt.

ET1

Timer 1 overflow interrupt Enable bit

Cleared to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

EX1

External interrupt 1 Enable bit

Cleared to disable external interrupt 1.

Set to enable external interrupt 1.

ET0

Timer 0 overflow interrupt Enable bit

Cleared to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

EX0

External interrupt 0 Enable bit

Cleared to disable external interrupt 0.

Set to enable external interrupt 0.

AT89C51ED2-RDTUM Datasheet(PDF) 74 Page - ATMEL Corporation

AT89C51ED2-RDTUM Datasheet(HTML) 74 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL