AT89C51ED2-RDTUM datasheet(81/137 Pages) ATMEL

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4235K–8051–05/08

AT89C51RD2/ED2

18.3

Power-Down Mode

The Power-Down mode places the AT89C51RD2/ED2 in a very low power state. Power-Down

mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering

Power-Down mode is preserved, i.e., the program counter, program status word register retain

their data for the duration of Power-Down mode. In addition, the SFR and RAM contents are pre-

served. The status of the Port pins during Power-Down mode is detailed in Table 18-1.

Note:

VCC may be reduced to as low as VRET during Power-Down mode to further reduce power dissi-

pation. Take care, however, that VDD is not reduced until Power-Down mode is invoked.

18.3.1

Entering Power-Down Mode

To enter Power-Down mode, set PD bit in PCON register. The AT89C51RD2/ED2 enters the

Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets

PD bit is the last instruction executed.

18.3.2

Exiting Power-Down Mode

Note:

If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is

restored to the normal operating level.

There are three ways to exit the Power-Down mode:

Generate an enabled external interrupt.

– The AT89C51RD2/ED2 provides capability to exit from Power-Down using INT0#,

INT1#.

Hardware clears PD bit in PCON register which starts the oscillator and restores the

clocks to the CPU and peripherals. Using INTx# input, execution resumes when the

input is released (see Figure 18-1). Execution resumes with the interrupt service

routine. Upon completion of the interrupt service routine, program execution

resumes with the instruction immediately following the instruction that activated

Power-Down mode.

Note:

The external interrupt used to exit Power-Down mode must be configured as level sensitive

(INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the inter-

rupt must be long enough to allow the oscillator to stabilize. The execution will only resume when

the interrupt is deasserted.

Note:

Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM content.

Figure 18-1. Power-Down Exit Waveform Using INT1:0#

Generate a reset.

– A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU and

peripherals. Program execution momentarily resumes with the instruction

immediately following the instruction that activated Power-Down mode and may

INT1:0#

OSC

Power-down phase

Oscillator restart phase

Active phase

AT89C51ED2-RDTUM Datasheet(PDF) 81 Page - ATMEL Corporation

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