AT89C51ED2-RDTUM datasheet(31/137 Pages) ATMEL

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4235K–8051–05/08

AT89C51RD2/ED2

Figure 12-1. Auto-reload Mode Up/Down Counter (DCEN = 1)

12.2

Programmable

Clock-output

In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock generator

(See Figure 12-2). The input clock increments TL2 at frequency FCLK PERIPH/2. The timer repeat-

edly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L

registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do not generate inter-

rupts. The formula gives the clock-out frequency as a function of the system oscillator frequency

and the value in the RCAP2H and RCAP2L registers:

For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz

(FCLK PERIPH/2

16) to 4 MHz (F

CLK PERIPH/4). The generated clock signal is brought out to T2 pin

(P1.0).

Timer 2 is programmed for the clock-out mode as follows:

• Set T2OE bit in T2MOD register.

• Clear C/T2 bit in T2CON register.

• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value

or a different one depending on the application.

• To start the timer, set TR2 run control bit in T2CON register.

(DOWN COUNTING RELOAD VALUE)

C/T2

TF2

TR2

EXF2

TH2

(8-bit)

TL2

(8-bit)

RCAP2H

(8-bit)

RCAP2L

(

8-bit)

FFh

(8-bit)

FFh

(8-bit)

TOGGLE

(UP COUNTING RELOAD VALUE)

TIMER 2

INTERRUPT

FCLK PERIPH

T2CON

T2EX:

If DCEN = 1, 1 = UP

If DCEN = 1, 0 = DOWN

If DCEN = 0, up counting

Clock O

–

utFrequency

CLKPERIPH

65536

RCAP

2H RCAP2L

⁄

)

–

(

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