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A32100DX-PLB Datasheet(PDF) 41 Page - Actel Corporation

Part # A32100DX-PLB
Description  Integrator Series FPGAs: 1200XL and 3200DX Families
PDF  84 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

A32100DX-PLB Datasheet(HTML) 41 Page - Actel Corporation

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Discontinued – v3.0
41
Integrato r Se ries F P G A s: 1200 XL and 320 0DX Fam ilies
A321 00DX Timing Char act eristics (continued)
(Worst-Case Commercial Conditions VCC = 4.75 V, TJ = 70°C)
‘–3 Speed
‘–2 Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
3.3V ‘Std’
Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
Logic Module Timing
Synchronous SRAM Operations
tRC
Read Cycle Time
6.4
7.5
8.5
10.0
14.3
11.7
ns
tWC
Write Cycle Time
6.4
7.5
8.5
10.0
14.3
11.7
ns
tRCKHL
Clock High/Low Time
3.2
3.8
4.3
5.0
7.1
5.9
ns
tRCO
Data Valid After Clock High/Low
3.2
3.8
4.3
5.0
7.1
5.9
ns
tADSU
Address/Data Set-Up Time
1.5
1.8
2.0
2.4
3.4
2.8
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
ns
tRENSU
Read Enable Set-Up
0.6
0.7
0.8
0.9
1.3
1.0
ns
tRENH
Read Enable Hold
3.2
3.8
4.3
5.0
7.1
5.9
ns
tWENSU
Write Enable Set-Up
2.6
3.0
3.4
4.0
5.7
4.7
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
0.0
ns
tBENS
Block Enable Set-Up
2.6
3.1
3.5
4.1
5.8
4.8
ns
tBENH
Block Enable Hold
0.0
0.0
0.0
0.0
0.0
0.0
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
7.7
9.0
10.2
12.0
17.2
14.1
ns
tRDADV
Read Address Valid
8.3
9.8
11.1
13.0
18.6
15.2
ns
tADSU
Address/Data Set-Up Time
1.5
1.8
2.0
2.4
3.4
2.8
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
ns
tRENSUA
Read Enable Set-Up to Address Valid
0.57
0.7
0.8
0.9
1.3
1.0
ns
tRENHA
Read Enable Hold
3.2
3.8
4.3
5.0
7.1
5.9
ns
tWENSU
Write Enable Set-Up
2.6
3.0
3.4
4.0
5.7
4.7
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
0.0
ns
tDOH
Data Out Hold Time
1.1
1.35
1.5
1.8
2.6
2.1
ns



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