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A32100DX-PLB Datasheet(PDF) 45 Page - Actel Corporation

Part # A32100DX-PLB
Description  Integrator Series FPGAs: 1200XL and 3200DX Families
PDF  84 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

A32100DX-PLB Datasheet(HTML) 45 Page - Actel Corporation

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Discontinued – v3.0
45
Integrato r Se ries F P G A s: 1200 XL and 320 0DX Fam ilies
A321 40DX Timing Char act eristics (continued)
(Worst-Case Commercial Conditions VCC = 4.75 V, TJ = 70°C)
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
3.3V ‘Std’
Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.2
1.6
1.9
2.4
2.2
ns
tINGO
Input Latch Gate-to-Output
2.3
3.1
3.7
4.7
4.3
ns
tINH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Latch Set-Up
0.3
0.4
0.47
0.6
0.55
ns
tILA
Latch Active Pulse Width
3.1
4.2
4.9
6.4
5.7
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
2.7
3.7
4.3
5.6
5.0
ns
tIRD2
FO=2 Routing Delay
3.1
4.2
4.9
6.4
5.7
ns
tIRD3
FO=3 Routing Delay
3.4
4.5
5.3
6.9
6.2
ns
tIRD4
FO=4 Routing Delay
3.9
5.2
6.1
7.9
7.1
ns
tIRD5
FO=8 Routing Delay
5.6
7.5
8.8
11.4
10.3
ns
tIRDD
Decode-to-Output Routing Delay
0.3
0.4
0.5
0.7
0.6
ns
Global Clock Network
tCKH
Input Low to High
FO=32
FO=486
6.2
6.8
8.3
9.1
9.7
10.7
12.7
13.9
11.4
12.5
ns
ns
tCKL
Input High to Low
FO=32
FO=486
6.12
6.7
8.2
8.9
9.6
10.5
12.5
13.6
11.3
12.3
ns
ns
tPW
Minimum Pulse Width
FO=32
FO=486
2.7
2.9
3.7
3.9
4.3
4.6
5.6
6.0
5.0
5.41
ns
ns
tCKSW
Maximum Skew
FO=32
FO=486
0.6
0.6
0.9
0.9
1.0
1.0
1.3
1.3
1.17
1.17
ns
ns
tSUEXT
Input Latch External Set-Up
FO=32
FO=486
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO=32
FO=486
2.2
2.2
2.9
2.9
3.4
3.4
4.4
4.4
4.0
4.0
ns
ns
tP
Minimum Period (1/fmax)
FO=32
FO=486
5.7
6.6
7.6
8.3
8.3
9.5
11.9
13.6
9.0
11.1
ns
ns
fMAX
Maximum Datapath Frequency
FO=32
FO=486
173
151
138
121
120
105
84
74
102
90
MHz
MHz
Note:
1.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.



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