ATmega16M1 datasheet(29/365 Pages) ATMEL

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7647F–AVR–04/09

ATmega16/32/64/M1/C1

System Clock

5.1

Clock Systems and their Distribution

Figure 5-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to unused

modules can be halted by using different sleep modes, as described in “Power Management and

Sleep Modes” on page 40. The clock systems are detailed below.

Figure 5-1.

Clock Distribution

5.1.1

CPU Clock – clk

CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

5.1.2

I/O Clock – clk

I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, UART. The

I/O clock is also used by the External Interrupt module, but note that some external interrupts

are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock

is halted.

General I/O

Modules

ADC

CPU Core

RAM

clk

I/O

AVR Clock

Control Unit

clk

CPU

Flash and

EEPROM

clk

FLASH

clk

ADC

Source Clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog Clock

Calibrated RC

Oscillator

(Crystal

Oscillator)

External Clock

Fast Peripherals

PLL

CLK

PLL

Multiplexer

PLL Input

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