ATtiny24-20SSU datasheet(39/236 Pages) ATMEL

39 / 236 page

8006H–AVR–10/09

ATtiny24/44/84

System Control and Reset

8.1

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative

Jump – instruction to the reset handling routine. If the program never enables an interrupt

source, the Interrupt Vectors are not used, and regular program code can be placed at these

locations. The circuit diagram in Figure 8-1 shows the reset logic. Electrical parameters of the

reset circuitry are given in Table 20-4 on page 177.

Figure 8-1.

Reset Logic

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-

ferent selections for the delay period are presented in “Clock Sources” on page 25.

MCU Status

Brown-out

Reset Circuit

BODLEVEL [2..0]

Delay Counters

CKSEL[3:0]

TIMEOUT

DATA BUS

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

Watchdog

Oscillator

SUT[1:0]

Power-on Reset

Circuit

ATtiny24-20SSU Datasheet(PDF) 39 Page - ATMEL Corporation