HCS12 datasheet(393/452 Pages) FREESCALE

393 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

393

TBL oprx0_xysp

(M) + [(B)

× ((M+1) – (M))] ⇒ A

8-Bit Table Lookup and Interpolate

Initialize B, and index before TBL.

<ea> points at first 8-bit table entry (M) and B is fractional part

of lookup value.

(no indirect addressing modes or extensions allowed)

IDX

18 3D xb

ORfffP

OrrffffP

– – – –

∆ ∆ – ∆

C Bit is undefined

in HC12

TBNE abdxys,rel9

If (cntr) not = 0, then Branch;

else Continue to next instruction

Test Counter and Branch if Not Zero

(cntr = A, B, D, X,Y, or SP)

REL

(9-bit)

04 lb rr

PPP (branch)

PPO (no

branch)

PPP

– – – –

TFR abcdxys,abcdxys

(r1)

⇒ r2 or

$00:(r1)

⇒ r2 or

(r1[7:0])

⇒ r2

Transfer Register to Register

r1 and r2 may be A, B, CCR, D, X, Y, or SP

INH

B7 eb

– – – –

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

TPA

(CCR)

⇒ A

Translates to TFR CCR ,A

INH

B7 20

– – – –

TRAP trapnum

(SP) – 2

⇒ SP;

RTNH:RTNL ⇒ M(SP):M(SP+1);

(SP) – 2

⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);

(SP) – 2

⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);

(SP) – 2

⇒ SP; (B:A) ⇒ M(SP):M(SP+1);

(SP) – 1

⇒ SP; (CCR) ⇒ M(SP)

⇒ I; (TRAP Vector) ⇒ PC

Unimplemented opcode trap

INH

18 tn

tn = $30–$39

$40–$FF

OVSPSSPSsP

OfVSPSSPSsP

– – – 1

– – – –

TST opr16a

TST oprx0_xysp

TST oprx9,xysp

TST oprx16,xysp

TST [D,xysp]

TST [oprx16,xysp]

TSTA

TSTB

(M) – 0

Test Memory for Zero or Minus

(A) – 0

Test A for Zero or Minus

(B) – 0

Test B for Zero or Minus

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

F7 hh ll

E7 xb

E7 xb ff

E7 xb ee ff

E7 xb

E7 xb ee ff

rPO

rPf

rPO

frPP

fIfrPf

fIPrPf

rOP

rfP

rPO

frPP

fIfrfP

fIPrfP

– – – –

∆ ∆ 0 0

TSX

(SP)

⇒ X

Translates to TFR SP,X

INH

B7 75

– – – –

TSY

(SP)

⇒ Y

Translates to TFR SP,Y

INH

B7 76

– – – –

TXS

(X)

⇒ SP

Translates to TFR X,SP

INH

B7 57

– – – –

TYS

(Y)

⇒ SP

Translates to TFR Y,SP

INH

B7 67

– – – –

WAI

(SP) – 2

⇒ SP;

RTNH:RTNL ⇒ M(SP):M(SP+1);

(SP) – 2

⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);

(SP) – 2

⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);

(SP) – 2

⇒ SP; (B:A) ⇒ M(SP):M(SP+1);

(SP) – 1

⇒ SP; (CCR) ⇒ M(SP);

WAIT for interrupt

INH

OSSSSsf

OSSSfSsf

– – – –

(after interrupt)

fVfPPP

VfPPP

– – – 1

– – – –

– 1 – 1

– – – –

Table A-1. Instruction Set Summary (Sheet 13 of 14)

Source Form

Operation

Addr.

Mode

Machine

Coding (hex)

Access Detail

S X H I

N Z V C

HCS12

M68HC12

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