HCS12 datasheet(391/452 Pages) FREESCALE

391 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

391

SBA

(A) – (B)

⇒ A

Subtract B from A

INH

18 16

– – – –

∆ ∆ ∆ ∆

SBCA #opr8i

SBCA opr8a

SBCA opr16a

SBCA oprx0_xysp

SBCA oprx9,xysp

SBCA oprx16,xysp

SBCA [D,xysp]

SBCA [oprx16,xysp]

(A) – (M) – C

⇒ A

Subtract with Borrow from A

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

82 ii

92 dd

B2 hh ll

A2 xb

A2 xb ff

A2 xb ee ff

A2 xb

A2 xb ee ff

rPf

rPO

rPf

rPO

frPP

fIfrPf

fIPrPf

rfP

rOP

rfP

rPO

frPP

fIfrfP

fIPrfP

– – – –

∆ ∆ ∆ ∆

SBCB #opr8i

SBCB opr8a

SBCB opr16a

SBCB oprx0_xysp

SBCB oprx9,xysp

SBCB oprx16,xysp

SBCB [D,xysp]

SBCB [oprx16,xysp]

(B) – (M) – C

⇒ B

Subtract with Borrow from B

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

C2 ii

D2 dd

F2 hh ll

E2 xb

E2 xb ff

E2 xb ee ff

E2 xb

E2 xb ee ff

rPf

rPO

rPf

rPO

frPP

fIfrPf

fIPrPf

rfP

rOP

rfP

rPO

frPP

fIfrfP

fIPrfP

– – – –

∆ ∆ ∆ ∆

SEC

⇒ C

Translates to ORCC #$01

IMM

14 01

– – – –

– – – 1

SEI

⇒ I; (inhibit I interrupts)

Translates to ORCC #$10

IMM

14 10

– – – 1

– – – –

SEV

⇒ V

Translates to ORCC #$02

IMM

14 02

– – – –

– – 1 –

SEX abc,dxys

$00:(r1)

⇒ r2 if r1, bit 7 is 0 or

$FF:(r1)

⇒ r2 if r1, bit 7 is 1

Sign Extend 8-bit r1 to 16-bit r2

r1 may be A, B, or CCR

r2 may be D, X, Y, or SP

Alternate mnemonic for TFR r1, r2

INH

B7 eb

– – – –

STAA opr8a

STAA opr16a

STAA oprx0_xysp

STAA oprx9,xysp

STAA oprx16,xysp

STAA [D,xysp]

STAA [oprx16,xysp]

(A)

⇒ M

Store Accumulator A to Memory

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

5A dd

7A hh ll

6A xb

6A xb ff

6A xb ee ff

6A xb

6A xb ee ff

PwO

PwP

PIfw

PIPw

wOP

PwO

PwP

PIfPw

PIPPw

– – – –

∆ ∆ 0 –

STAB opr8a

STAB opr16a

STAB oprx0_xysp

STAB oprx9,xysp

STAB oprx16,xysp

STAB [D,xysp]

STAB [oprx16,xysp]

(B)

⇒ M

Store Accumulator B to Memory

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

5B dd

7B hh ll

6B xb

6B xb ff

6B xb ee ff

6B xb

6B xb ee ff

PwO

PwP

PIfw

PIPw

wOP

PwO

PwP

PIfPw

PIPPw

– – – –

∆ ∆ 0 –

STD opr8a

STD opr16a

STD oprx0_xysp

STD oprx9,xysp

STD oprx16,xysp

STD [D,xysp]

STD [oprx16,xysp]

(A)

⇒ M, (B) ⇒ M+1

Store Double Accumulator

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

5C dd

7C hh ll

6C xb

6C xb ff

6C xb ee ff

6C xb

6C xb ee ff

PWO

PWP

PIfW

PIPW

WOP

PWO

PWP

PIfPW

PIPPW

– – – –

∆ ∆ 0 –

STOP

(SP) – 2

⇒ SP;

RTNH:RTNL ⇒ M(SP):M(SP+1);

(SP) – 2

⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);

(SP) – 2

⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);

(SP) – 2

⇒ SP; (B:A) ⇒ M(SP):M(SP+1);

(SP) – 1

⇒ SP; (CCR) ⇒ M(SP);

STOP All Clocks

Registers stacked to allow quicker recovery by interrupt.

If S control bit = 1, the STOP instruction is disabled and acts

like a two-cycle NOP.

INH

18 3E

(entering STOP)

– – – –

OOSSSSsf

OOSSSfSs

(exiting STOP)

fVfPPP

(continue)

(if STOP disabled)

Table A-1. Instruction Set Summary (Sheet 11 of 14)

Source Form

Operation

Addr.

Mode

Machine

Coding (hex)

Access Detail

S X H I

N Z V C

HCS12

M68HC12

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