HCS12 datasheet(392/452 Pages) FREESCALE

392 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

392

Freescale Semiconductor

STS opr8a

STS opr16a

STS oprx0_xysp

STS oprx9,xysp

STS oprx16,xysp

STS [D,xysp]

STS [oprx16,xysp]

(SPH:SPL) ⇒ M:M+1

Store Stack Pointer

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

5F dd

7F hh ll

6F xb

6F xb ff

6F xb ee ff

6F xb

6F xb ee ff

PWO

PWP

PIfW

PIPW

WOP

PWO

PWP

PIfPW

PIPPW

– – – –

∆ ∆ 0 –

STX opr8a

STX opr16a

STX oprx0_xysp

STX oprx9,xysp

STX oprx16,xysp

STX [D,xysp]

STX [oprx16,xysp]

(XH:XL) ⇒ M:M+1

Store Index Register X

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

5E dd

7E hh ll

6E xb

6E xb ff

6E xb ee ff

6E xb

6E xb ee ff

PWO

PWP

PIfW

PIPW

WOP

PWO

PWP

PIfPW

PIPPW

– – – –

∆ ∆ 0 –

STY opr8a

STY opr16a

STY oprx0_xysp

STY oprx9,xysp

STY oprx16,xysp

STY [D,xysp]

STY [oprx16,xysp]

(YH:YL) ⇒ M:M+1

Store Index Register Y

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

5D dd

7D hh ll

6D xb

6D xb ff

6D xb ee ff

6D xb

6D xb ee ff

PWO

PWP

PIfW

PIPW

WOP

PWO

PWP

PIfPW

PIPPW

– – – –

∆ ∆ 0 –

SUBA #opr8i

SUBA opr8a

SUBA opr16a

SUBA oprx0_xysp

SUBA oprx9,xysp

SUBA oprx16,xysp

SUBA [D,xysp]

SUBA [oprx16,xysp]

(A) – (M)

⇒ A

Subtract Memory from Accumulator A

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

80 ii

90 dd

B0 hh ll

A0 xb

A0 xb ff

A0 xb ee ff

A0 xb

A0 xb ee ff

rPf

rPO

rPf

rPO

frPP

fIfrPf

fIPrPf

rfP

rOP

rfP

rPO

frPP

fIfrfP

fIPrfP

– – – –

∆ ∆ ∆ ∆

SUBB #opr8i

SUBB opr8a

SUBB opr16a

SUBB oprx0_xysp

SUBB oprx9,xysp

SUBB oprx16,xysp

SUBB [D,xysp]

SUBB [oprx16,xysp]

(B) – (M)

⇒ B

Subtract Memory from Accumulator B

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

C0 ii

D0 dd

F0 hh ll

E0 xb

E0 xb ff

E0 xb ee ff

E0 xb

E0 xb ee ff

rPf

rPO

rPf

rPO

frPP

fIfrPf

fIPrPf

rfP

rOP

rfP

rPO

frPP

fIfrfP

fIPrfP

– – – –

∆ ∆ ∆ ∆

SUBD #opr16i

SUBD opr8a

SUBD opr16a

SUBD oprx0_xysp

SUBD oprx9,xysp

SUBD oprx16,xysp

SUBD [D,xysp]

SUBD [oprx16,xysp]

(D) – (M:M+1)

⇒ D

Subtract Memory from D (A:B)

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

83 jj kk

93 dd

B3 hh ll

A3 xb

A3 xb ff

A3 xb ee ff

A3 xb

A3 xb ee ff

RPf

RPO

RPf

RPO

fRPP

fIfRPf

fIPRPf

RfP

ROP

RfP

RPO

fRPP

fIfRfP

fIPRfP

– – – –

∆ ∆ ∆ ∆

SWI

(SP) – 2

⇒ SP;

RTNH:RTNL ⇒ M(SP):M(SP+1);

(SP) – 2

⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);

(SP) – 2

⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);

(SP) – 2

⇒ SP; (B:A) ⇒ M(SP):M(SP+1);

(SP) – 1

⇒ SP; (CCR) ⇒ M(SP)

⇒ I; (SWI Vector) ⇒ PC

Software Interrupt

INH

VSPSSPSsP*

– – – 1

– – – –

(for Reset)

1 1 – 1

– – – –

VfPPP

*The CPU also uses the SWI microcode sequence for hardware interrupts and unimplemented opcode traps. Reset uses the VfPPP variation of this sequence.

TAB

(A)

⇒ B

Transfer A to B

INH

18 0E

– – – –

∆ ∆ 0 –

TAP

(A)

⇒ CCR

Translates to TFR A , CCR

INH

B7 02

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

TBA

(B)

⇒ A

Transfer B to A

INH

18 0F

– – – –

∆ ∆ 0 –

TBEQ abdxys,rel9

If (cntr) = 0, then Branch;

else Continue to next instruction

Test Counter and Branch if Zero

(cntr = A, B, D, X,Y, or SP)

REL

(9-bit)

04 lb rr

PPP (branch)

PPO (no

branch)

PPP

– – – –

Table A-1. Instruction Set Summary (Sheet 12 of 14)

Source Form

Operation

Addr.

Mode

Machine

Coding (hex)

Access Detail

S X H I

N Z V C

HCS12

M68HC12

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