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HCS12 Datasheet(PDF) 388 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 388 Page - Freescale Semiconductor, Inc |
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388 / 452 page ![]() S12CPUV2 Reference Manual, Rev. 4.0 388 Freescale Semiconductor LDY #opr16i LDY opr8a LDY opr16a LDY oprx0_xysp LDY oprx9,xysp LDY oprx16,xysp LDY [D,xysp] LDY [oprx16,xysp] (M:M+1) ⇒ Y Load Index Register Y IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] CD jj kk DD dd FD hh ll ED xb ED xb ff ED xb ee ff ED xb ED xb ee ff PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP – – – – ∆ ∆ 0 – LEAS oprx0_xysp LEAS oprx9,xysp LEAS oprx16,xysp Effective Address ⇒ SP Load Effective Address into SP IDX IDX1 IDX2 1B xb 1B xb ff 1B xb ee ff Pf PO PP PP 1 PO PP – – – – – – – – LEAX oprx0_xysp LEAX oprx9,xysp LEAX oprx16,xysp Effective Address ⇒ X Load Effective Address into X IDX IDX1 IDX2 1A xb 1A xb ff 1A xb ee ff Pf PO PP PP 1 PO PP – – – – – – – – LEAY oprx0_xysp LEAY oprx9,xysp LEAY oprx16,xysp Effective Address ⇒ Y Load Effective Address into Y IDX IDX1 IDX2 19 xb 19 xb ff 19 xb ee ff Pf PO PP PP 1 PO PP – – – – – – – – LSL opr16a LSL oprx0_xysp LSL oprx9,xysp LSL oprx16,xysp LSL [D,xysp] LSL [oprx16,xysp] LSLA LSLB Logical Shift Left same function as ASL Logical Shift Accumulator A to Left Logical Shift Accumulator B to Left EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH 78 hh ll 68 xb 68 xb ff 68 xb ee ff 68 xb 68 xb ee ff 48 58 rPwO rPw rPwO frPPw fIfrPw fIPrPw O O rOPw rPw rPOw frPPw fIfrPw fIPrPw O O – – – – ∆ ∆ ∆ ∆ LSLD Logical Shift Left D Accumulator same function as ASLD INH 59 OO – – – – ∆ ∆ ∆ ∆ LSR opr16a LSR oprx0_xysp LSR oprx9,xysp LSR oprx16,xysp LSR [D,xysp] LSR [oprx16,xysp] LSRA LSRB Logical Shift Right Logical Shift Accumulator A to Right Logical Shift Accumulator B to Right EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH 74 hh ll 64 xb 64 xb ff 64 xb ee ff 64 xb 64 xb ee ff 44 54 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O rOPw rPw rPOw frPPw fIfrPw fIPrPw O O – – – – 0 ∆ ∆ ∆ LSRD Logical Shift Right D Accumulator INH 49 OO – – – – 0 ∆ ∆ ∆ MAXA oprx0_xysp MAXA oprx9,xysp MAXA oprx16,xysp MAXA [D,xysp] MAXA [oprx16,xysp] MAX((A), (M)) ⇒ A MAX of 2 Unsigned 8-Bit Values N, Z, V and C status bits reflect result of internal compare ((A) – (M)). IDX IDX1 IDX2 [D,IDX] [IDX2] 18 18 xb 18 18 xb ff 18 18 xb ee ff 18 18 xb 18 18 xb ee ff OrPf OrPO OfrPP OfIfrPf OfIPrPf OrfP OrPO OfrPP OfIfrfP OfIPrfP – – – – ∆ ∆ ∆ ∆ Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. MAXM oprx0_xysp MAXM oprx9,xysp MAXM oprx16,xysp MAXM [D,xysp] MAXM [oprx16,xysp] MAX((A), (M)) ⇒ M MAX of 2 Unsigned 8-Bit Values N, Z, V and C status bits reflect result of internal compare ((A) – (M)). IDX IDX1 IDX2 [D,IDX] [IDX2] 18 1C xb 18 1C xb ff 18 1C xb ee ff 18 1C xb 18 1C xb ee ff OrPw OrPwO OfrPwP OfIfrPw OfIPrPw OrPw OrPwO OfrPwP OfIfrPw OfIPrPw – – – – ∆ ∆ ∆ ∆ MEM µ (grade) ⇒ M(Y); (X) + 4 ⇒ X; (Y) + 1 ⇒ Y; A unchanged if (A) < P1 or (A) > P2 then µ = 0, else µ = MIN[((A) – P1)×S1, (P2 – (A))×S2, $FF] where: A = current crisp input value; X points at 4-byte data structure that describes a trapezoidal membership function (P1, P2, S1, S2); Y points at fuzzy input (RAM location). See CPU12 Reference Manual for special cases. Special 01 RRfOw RRfOw – – ? – ? ? ? ? Table A-1. Instruction Set Summary (Sheet 8 of 14) Source Form Operation Addr. Mode Machine Coding (hex) Access Detail S X H I N Z V C HCS12 M68HC12 C 0 b7 b0 C 0 b7 b0 A B b7 b0 C 0 b7 b0 C 0 b7 b0 A B b7 b0 |
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