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HCS12 Datasheet(PDF) 389 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 389 Page - Freescale Semiconductor, Inc |
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389 / 452 page  S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 389 MINA oprx0_xysp MINA oprx9,xysp MINA oprx16,xysp MINA [D,xysp] MINA [oprx16,xysp] MIN((A), (M)) ⇒ A MIN of 2 Unsigned 8-Bit Values N, Z, V and C status bits reflect result of internal compare ((A) – (M)). IDX IDX1 IDX2 [D,IDX] [IDX2] 18 19 xb 18 19 xb ff 18 19 xb ee ff 18 19 xb 18 19 xb ee ff OrPf OrPO OfrPP OfIfrPf OfIPrPf OrfP OrPO OfrPP OfIfrfP OfIPrfP – – – – ∆ ∆ ∆ ∆ MINM oprx0_xysp MINM oprx9,xysp MINM oprx16,xysp MINM [D,xysp] MINM [oprx16,xysp] MIN((A), (M)) ⇒ M MIN of 2 Unsigned 8-Bit Values N, Z, V and C status bits reflect result of internal compare ((A) – (M)). IDX IDX1 IDX2 [D,IDX] [IDX2] 18 1D xb 18 1D xb ff 18 1D xb ee ff 18 1D xb 18 1D xb ee ff OrPw OrPwO OfrPwP OfIfrPw OfIPrPw OrPw OrPwO OfrPwP OfIfrPw OfIPrPw – – – – ∆ ∆ ∆ ∆ MOVB #opr8, opr16a1 MOVB #opr8i, oprx0_xysp1 MOVB opr16a, opr16a1 MOVB opr16a, oprx0_xysp1 MOVB oprx0_xysp, opr16a1 MOVB oprx0_xysp, oprx0_xysp1 (M1) ⇒ M2 Memory to Memory Byte-Move (8-Bit) IMM-EXT IMM-IDX EXT-EXT EXT-IDX IDX-EXT IDX-IDX 18 0B ii hh ll 18 08 xb ii 18 0C hh ll hh ll 18 09 xb hh ll 18 0D xb hh ll 18 0A xb xb OPwP OPwO OrPwPO OPrPw OrPwP OrPwO OPwP OPwO OrPwPO OPrPw OrPwP OrPwO – – – – – – – – MOVW #oprx16, opr16a1 MOVW #opr16i, oprx0_xysp1 MOVW opr16a, opr16a1 MOVW opr16a, oprx0_xysp1 MOVW oprx0_xysp, opr16a1 MOVW oprx0_xysp, oprx0_xysp1 (M:M+11) ⇒ M:M+12 Memory to Memory Word-Move (16-Bit) IMM-EXT IMM-IDX EXT-EXT EXT-IDX IDX-EXT IDX-IDX 18 03 jj kk hh ll 18 00 xb jj kk 18 04 hh ll hh ll 18 01 xb hh ll 18 05 xb hh ll 18 02 xb xb OPWPO OPPW ORPWPO OPRPW ORPWP ORPWO OPWPO OPPW ORPWPO OPRPW ORPWP ORPWO – – – – – – – – MUL (A) × (B) ⇒ A:B 8 by 8 Unsigned Multiply INH 12 O ffO – – – – – – – ∆ NEG opr16a NEG oprx0_xysp NEG oprx9,xysp NEG oprx16,xysp NEG [D,xysp] NEG [oprx16,xysp] NEGA NEGB 0 – (M) ⇒ M equivalent to (M) + 1 ⇒ M Two’s Complement Negate 0 – (A) ⇒ A equivalent to (A) + 1 ⇒ A Negate Accumulator A 0 – (B) ⇒ B equivalent to (B) + 1 ⇒ B Negate Accumulator B EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH 70 hh ll 60 xb 60 xb ff 60 xb ee ff 60 xb 60 xb ee ff 40 50 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O rOPw rPw rPOw frPPw fIfrPw fIPrPw O O – – – – ∆ ∆ ∆ ∆ NOP No Operation INH A7 OO – – – – – – – – ORAA #opr8i ORAA opr8a ORAA opr16a ORAA oprx0_xysp ORAA oprx9,xysp ORAA oprx16,xysp ORAA [D,xysp] ORAA [oprx16,xysp] (A) + (M) ⇒ A Logical OR A with Memory IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] 8A ii 9A dd BA hh ll AA xb AA xb ff AA xb ee ff AA xb AA xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – – – ∆ ∆ 0 – Note 1. The first operand in the source code statement specifies the source for the move. ORAB #opr8i ORAB opr8a ORAB opr16a ORAB oprx0_xysp ORAB oprx9,xysp ORAB oprx16,xysp ORAB [D,xysp] ORAB [oprx16,xysp] (B) + (M) ⇒ B Logical OR B with Memory IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] CA ii DA dd FA hh ll EA xb EA xb ff EA xb ee ff EA xb EA xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – – – ∆ ∆ 0 – ORCC #opr8i (CCR) + M ⇒ CCR Logical OR CCR with Memory IMM 14 ii PP ⇑ – ⇑ ⇑ ⇑ ⇑ ⇑ ⇑ PSHA (SP) – 1 ⇒ SP; (A) ⇒ M(SP) Push Accumulator A onto Stack INH 36 Os Os – – – – – – – – PSHB (SP) – 1 ⇒ SP; (B) ⇒ M(SP) Push Accumulator B onto Stack INH 37 Os Os – – – – – – – – PSHC (SP) – 1 ⇒ SP; (CCR) ⇒ M(SP) Push CCR onto Stack INH 39 Os Os – – – – – – – – PSHD (SP) – 2 ⇒ SP; (A:B) ⇒ M(SP):M(SP+1) Push D Accumulator onto Stack INH 3B OS OS – – – – – – – – PSHX (SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1) Push Index Register X onto Stack INH 34 OS OS – – – – – – – – PSHY (SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1) Push Index Register Y onto Stack INH 35 OS OS – – – – – – – – Table A-1. Instruction Set Summary (Sheet 9 of 14) Source Form Operation Addr. Mode Machine Coding (hex) Access Detail S X H I N Z V C HCS12 M68HC12 |
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