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HCS12 Datasheet(PDF) 387 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 387 Page - Freescale Semiconductor, Inc |
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387 / 452 page  S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 387 LBGT rel16 Long Branch if Greater Than (if Z + (N ⊕ V) = 0) (signed) REL 18 2E qq rr OPPP/OPO 1 OPPP/OPO 1 – – – – – – – – LBHI rel16 Long Branch if Higher (if C + Z = 0) (unsigned) REL 18 22 qq rr OPPP/OPO 1 OPPP/OPO 1 – – – – – – – – LBHS rel16 Long Branch if Higher or Same (if C = 0) (unsigned) same function as LBCC REL 18 24 qq rr OPPP/OPO 1 OPPP/OPO 1 – – – – – – – – LBLE rel16 Long Branch if Less Than or Equal (if Z + (N ⊕ V) = 1) (signed) REL 18 2F qq rr OPPP/OPO 1 OPPP/OPO 1 – – – – – – – – LBLO rel16 Long Branch if Lower (if C = 1) (unsigned) same function as LBCS REL 18 25 qq rr OPPP/OPO 1 OPPP/OPO 1 – – – – – – – – LBLS rel16 Long Branch if Lower or Same (if C + Z = 1) (unsigned) REL 18 23 qq rr OPPP/OPO 1 OPPP/OPO 1 – – – – – – – – LBLT rel16 Long Branch if Less Than (if N ⊕ V = 1) (signed) REL 18 2D qq rr OPPP/OPO 1 OPPP/OPO 1 – – – – – – – – LBMI rel16 Long Branch if Minus (if N = 1) REL 18 2B qq rr OPPP/OPO 1 OPPP/OPO 1 – – – – – – – – LBNE rel16 Long Branch if Not Equal (if Z = 0) REL 18 26 qq rr OPPP/OPO 1 OPPP/OPO 1 – – – – – – – – LBPL rel16 Long Branch if Plus (if N = 0) REL 18 2A qq rr OPPP/OPO 1 OPPP/OPO 1 – – – – – – – – LBRA rel16 Long Branch Always (if 1=1) REL 18 20 qq rr OPPP OPPP – – – – – – – – LBRN rel16 Long Branch Never (if 1 = 0) REL 18 21 qq rr OPO OPO – – – – – – – – LBVC rel16 Long Branch if Overflow Bit Clear (if V=0) REL 18 28 qq rr OPPP/OPO 1 OPPP/OPO 1 – – – – – – – – LBVS rel16 Long Branch if Overflow Bit Set (if V = 1) REL 18 29 qq rr OPPP/OPO 1 OPPP/OPO 1 – – – – – – – – LDAA #opr8i LDAA opr8a LDAA opr16a LDAA oprx0_xysp LDAA oprx9,xysp LDAA oprx16,xysp LDAA [D,xysp] LDAA [oprx16,xysp] (M) ⇒ A Load Accumulator A IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] 86 ii 96 dd B6 hh ll A6 xb A6 xb ff A6 xb ee ff A6 xb A6 xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – – – ∆ ∆ 0 – LDAB #opr8i LDAB opr8a LDAB opr16a LDAB oprx0_xysp LDAB oprx9,xysp LDAB oprx16,xysp LDAB [D,xysp] LDAB [oprx16,xysp] (M) ⇒ B Load Accumulator B IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] C6 ii D6 dd F6 hh ll E6 xb E6 xb ff E6 xb ee ff E6 xb E6 xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – – – ∆ ∆ 0 – LDD #opr16i LDD opr8a LDD opr16a LDD oprx0_xysp LDD oprx9,xysp LDD oprx16,xysp LDD [D,xysp] LDD [oprx16,xysp] (M:M+1) ⇒ A:B Load Double Accumulator D (A:B) IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] CC jj kk DC dd FC hh ll EC xb EC xb ff EC xb ee ff EC xb EC xb ee ff PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP – – – – ∆ ∆ 0 – Note 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken. LDS #opr16i LDS opr8a LDS opr16a LDS oprx0_xysp LDS oprx9,xysp LDS oprx16,xysp LDS [D,xysp] LDS [oprx16,xysp] (M:M+1) ⇒ SP Load Stack Pointer IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] CF jj kk DF dd FF hh ll EF xb EF xb ff EF xb ee ff EF xb EF xb ee ff PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP – – – – ∆ ∆ 0 – LDX #opr16i LDX opr8a LDX opr16a LDX oprx0_xysp LDX oprx9,xysp LDX oprx16,xysp LDX [D,xysp] LDX [oprx16,xysp] (M:M+1) ⇒ X Load Index Register X IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] CE jj kk DE dd FE hh ll EE xb EE xb ff EE xb ee ff EE xb EE xb ee ff PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP – – – – ∆ ∆ 0 – Table A-1. Instruction Set Summary (Sheet 7 of 14) Source Form Operation Addr. Mode Machine Coding (hex) Access Detail S X H I N Z V C HCS12 M68HC12 |
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