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HCS12 Datasheet(PDF) 383 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 383 Page - Freescale Semiconductor, Inc |
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383 / 452 page  S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 383 BLS rel8 Branch if Lower or Same (if C + Z = 1) (unsigned) REL 23 rr PPP/P 1 PPP/P 1 – – – – – – – – BLT rel8 Branch if Less Than (if N ⊕ V = 1) (signed) REL 2D rr PPP/P 1 PPP/P 1 – – – – – – – – BMI rel8 Branch if Minus (if N = 1) REL 2B rr PPP/P 1 PPP/P 1 – – – – – – – – BNE rel8 Branch if Not Equal (if Z = 0) REL 26 rr PPP/P 1 PPP/P 1 – – – – – – – – BPL rel8 Branch if Plus (if N = 0) REL 2A rr PPP/P 1 PPP/P 1 – – – – – – – – BRA rel8 Branch Always (if 1 = 1) REL 20 rr PPP PPP – – – – – – – – BRCLR opr8a, msk8, rel8 BRCLR opr16a, msk8, rel8 BRCLR oprx0_xysp, msk8, rel8 BRCLR oprx9,xysp, msk8, rel8 BRCLR oprx16,xysp, msk8, rel8 Branch if (M) • (mm) = 0 (if All Selected Bit(s) Clear) DIR EXT IDX IDX1 IDX2 4F dd mm rr 1F hh ll mm rr 0F xb mm rr 0F xb ff mm rr 0F xb ee ff mm rr rPPP rfPPP rPPP rfPPP PrfPPP rPPP rfPPP rPPP rffPPP frPffPPP – – – – – – – – BRN rel8 Branch Never (if 1 = 0) REL 21 rr PP – – – – – – – – BRSET opr8, msk8, rel8 BRSET opr16a, msk8, rel8 BRSET oprx0_xysp, msk8, rel8 BRSET oprx9,xysp, msk8, rel8 BRSET oprx16,xysp, msk8, rel8 Branch if (M) • (mm) = 0 (if All Selected Bit(s) Set) DIR EXT IDX IDX1 IDX2 4E dd mm rr 1E hh ll mm rr 0E xb mm rr 0E xb ff mm rr 0E xb ee ff mm rr rPPP rfPPP rPPP rfPPP PrfPPP rPPP rfPPP rPPP rffPPP frPffPPP – – – – – – – – BSET opr8, msk8 BSET opr16a, msk8 BSET oprx0_xysp, msk8 BSET oprx9,xysp, msk8 BSET oprx16,xysp, msk8 (M) + (mm) ⇒ M Set Bit(s) in Memory DIR EXT IDX IDX1 IDX2 4C dd mm 1C hh ll mm 0C xb mm 0C xb ff mm 0C xb ee ff mm rPwO rPwP rPwO rPwP frPwPO rPOw rPPw rPOw rPwP frPwOP – – – – ∆ ∆ 0 – BSR rel8 (SP) – 2 ⇒ SP; RTNH:RTNL ⇒ M(SP):M(SP+1) Subroutine address ⇒ PC Branch to Subroutine REL 07 rr SPPP PPPS – – – – – – – – BVC rel8 Branch if Overflow Bit Clear (if V = 0) REL 28 rr PPP/P 1 PPP/P 1 – – – – – – – – BVS rel8 Branch if Overflow Bit Set (if V = 1) REL 29 rr PPP/P 1 PPP/P 1 – – – – – – – – CALL opr16a, page CALL oprx0_xysp, page CALL oprx9,xysp, page CALL oprx16,xysp, page CALL [D,xysp] CALL [oprx16, xysp] (SP) – 2 ⇒ SP; RTNH:RTNL ⇒ M(SP):M(SP+1) (SP) – 1 ⇒ SP; (PPG) ⇒ M(SP); pg ⇒ PPAGE register; Program address ⇒ PC Call subroutine in extended memory (Program may be located on another expansion memory page.) Indirect modes get program address and new pg value based on pointer. EXT IDX IDX1 IDX2 [D,IDX] [IDX2] 4A hh ll pg 4B xb pg 4B xb ff pg 4B xb ee ff pg 4B xb 4B xb ee ff gnSsPPP gnSsPPP gnSsPPP fgnSsPPP fIignSsPPP fIignSsPPP gnfSsPPP gnfSsPPP gnfSsPPP fgnfSsPPP fIignSsPPP fIignSsPPP – – – – – – – – CBA (A) – (B) Compare 8-Bit Accumulators INH 18 17 OO OO – – – – ∆ ∆ ∆ ∆ CLC 0 ⇒ C Translates to ANDCC #$FE IMM 10 FE PP – – – – – – – 0 CLI 0 ⇒ I Translates to ANDCC #$EF (enables I-bit interrupts) IMM 10 EF PP – – – 0 – – – – CLR opr16a CLR oprx0_xysp CLR oprx9,xysp CLR oprx16,xysp CLR [D,xysp] CLR [oprx16,xysp] CLRA CLRB 0 ⇒ M Clear Memory Location 0 ⇒ A Clear Accumulator A 0 ⇒ B Clear Accumulator B EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH 79 hh ll 69 xb 69 xb ff 69 xb ee ff 69 xb 69 xb ee ff 87 C7 PwO Pw PwO PwP PIfw PIPw O O wOP Pw PwO PwP PIfPw PIPPw O O – – – – 0 1 0 0 CLV 0 ⇒ V Translates to ANDCC #$FD IMM 10 FD PP – – – – – – 0 – Note 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken. CMPA #opr8i CMPA opr8a CMPA opr16a CMPA oprx0_xysp CMPA oprx9,xysp CMPA oprx16,xysp CMPA [D,xysp] CMPA [oprx16,xysp] (A) – (M) Compare Accumulator A with Memory IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] 81 ii 91 dd B1 hh ll A1 xb A1 xb ff A1 xb ee ff A1 xb A1 xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – – – ∆ ∆ ∆ ∆ Table A-1. Instruction Set Summary (Sheet 3 of 14) Source Form Operation Addr. Mode Machine Coding (hex) Access Detail S X H I N Z V C HCS12 M68HC12 |
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