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HCS12 Datasheet(PDF) 385 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 385 Page - Freescale Semiconductor, Inc |
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385 / 452 page ![]() S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 385 DEC opr16a DEC oprx0_xysp DEC oprx9,xysp DEC oprx16,xysp DEC [D,xysp] DEC [oprx16,xysp] DECA DECB (M) – $01 ⇒ M Decrement Memory Location (A) – $01 ⇒ A Decrement A (B) – $01 ⇒ B Decrement B EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH 73 hh ll 63 xb 63 xb ff 63 xb ee ff 63 xb 63 xb ee ff 43 53 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O rOPw rPw rPOw frPPw fIfrPw fIPrPw O O – – – – ∆ ∆ ∆ – DES (SP) – $0001 ⇒ SP Translates to LEAS –1,SP IDX 1B 9F Pf PP 1 – – – – – – – – DEX (X) – $0001 ⇒ X Decrement Index Register X INH 09 OO – – – – – ∆ – – DEY (Y) – $0001 ⇒ Y Decrement Index Register Y INH 03 OO – – – – – ∆ – – EDIV (Y:D) ÷ (X) ⇒ Y Remainder ⇒ D 32 by 16 Bit ⇒ 16 Bit Divide (unsigned) INH 11 ffffffffffO ffffffffffO – – – – ∆ ∆ ∆ ∆ EDIVS (Y:D) ÷ (X) ⇒ Y Remainder ⇒ D 32 by 16 Bit ⇒ 16 Bit Divide (signed) INH 18 14 OffffffffffO OffffffffffO – – – – ∆ ∆ ∆ ∆ EMACS opr16a 2 (M(X):M(X+1)) × (M(Y):M(Y+1)) + (M~M+3) ⇒ M~M+3 16 by 16 Bit ⇒ 32 Bit Multiply and Accumulate (signed) Special 18 12 hh ll ORROfffRRfWWP ORROfffRRfWWP – – – – ∆ ∆ ∆ ∆ EMAXD oprx0_xysp EMAXD oprx9,xysp EMAXD oprx16,xysp EMAXD [D,xysp] EMAXD [oprx16,xysp] MAX((D), (M:M+1)) ⇒ D MAX of 2 Unsigned 16-Bit Values N, Z, V and C status bits reflect result of internal compare ((D) – (M:M+1)) IDX IDX1 IDX2 [D,IDX] [IDX2] 18 1A xb 18 1A xb ff 18 1A xb ee ff 18 1A xb 18 1A xb ee ff ORPf ORPO OfRPP OfIfRPf OfIPRPf ORfP ORPO OfRPP OfIfRfP OfIPRfP – – – – ∆ ∆ ∆ ∆ EMAXM oprx0_xysp EMAXM oprx9,xysp EMAXM oprx16,xysp EMAXM [D,xysp] EMAXM [oprx16,xysp] MAX((D), (M:M+1)) ⇒ M:M+1 MAX of 2 Unsigned 16-Bit Values N, Z, V and C status bits reflect result of internal compare ((D) – (M:M+1)) IDX IDX1 IDX2 [D,IDX] [IDX2] 18 1E xb 18 1E xb ff 18 1E xb ee ff 18 1E xb 18 1E xb ee ff ORPW ORPWO OfRPWP OfIfRPW OfIPRPW ORPW ORPWO OfRPWP OfIfRPW OfIPRPW – – – – ∆ ∆ ∆ ∆ EMIND oprx0_xysp EMIND oprx9,xysp EMIND oprx16,xysp EMIND [D,xysp] EMIND [oprx16,xysp] MIN((D), (M:M+1)) ⇒ D MIN of 2 Unsigned 16-Bit Values N, Z, V and C status bits reflect result of internal compare ((D) – (M:M+1)) IDX IDX1 IDX2 [D,IDX] [IDX2] 18 1B xb 18 1B xb ff 18 1B xb ee ff 18 1B xb 18 1B xb ee ff ORPf ORPO OfRPP OfIfRPf OfIPRPf ORfP ORPO OfRPP OfIfRfP OfIPRfP – – – – ∆ ∆ ∆ ∆ EMINM oprx0_xysp EMINM oprx9,xysp EMINM oprx16,xysp EMINM [D,xysp] EMINM [oprx16,xysp] MIN((D), (M:M+1)) ⇒ M:M+1 MIN of 2 Unsigned 16-Bit Values N, Z, V and C status bits reflect result of internal compare ((D) – (M:M+1)) IDX IDX1 IDX2 [D,IDX] [IDX2] 18 1F xb 18 1F xb ff 18 1F xb ee ff 18 1F xb 18 1F xb ee ff ORPW ORPWO OfRPWP OfIfRPW OfIPRPW ORPW ORPWO OfRPWP OfIfRPW OfIPRPW – – – – ∆ ∆ ∆ ∆ EMUL (D) × (Y) ⇒ Y:D 16 by 16 Bit Multiply (unsigned) INH 13 ffO ffO – – – – ∆ ∆ – ∆ EMULS (D) × (Y) ⇒ Y:D 16 by 16 Bit Multiply (signed) INH 18 13 OfO OfO – – – – ∆ ∆ – ∆ (if followed by page 2 instruction) OffO OfO EORA #opr8i EORA opr8a EORA opr16a EORA oprx0_xysp EORA oprx9,xysp EORA oprx16,xysp EORA [D,xysp] EORA [oprx16,xysp] (A) ⊕ (M) ⇒ A Exclusive-OR A with Memory IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] 88 ii 98 dd B8 hh ll A8 xb A8 xb ff A8 xb ee ff A8 xb A8 xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – – – ∆ ∆ 0 – Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. 2. opr16a is an extended address specification. Both X and Y point to source operands. EORB #opr8i EORB opr8a EORB opr16a EORB oprx0_xysp EORB oprx9,xysp EORB oprx16,xysp EORB [D,xysp] EORB [oprx16,xysp] (B) ⊕ (M) ⇒ B Exclusive-OR B with Memory IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] C8 ii D8 dd F8 hh ll E8 xb E8 xb ff E8 xb ee ff E8 xb E8 xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – – – ∆ ∆ 0 – Table A-1. Instruction Set Summary (Sheet 5 of 14) Source Form Operation Addr. Mode Machine Coding (hex) Access Detail S X H I N Z V C HCS12 M68HC12 |
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