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HCS12 Datasheet(PDF) 381 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 381 Page - Freescale Semiconductor, Inc |
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381 / 452 page  S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 381 Table A-1. Instruction Set Summary (Sheet 1 of 14) Source Form Operation Addr. Mode Machine Coding (hex) Access Detail S X H I N Z V C HCS12 M68HC12 ABA (A) + (B) ⇒ A Add Accumulators A and B INH 18 06 OO OO – – ∆ – ∆ ∆ ∆ ∆ ABX (B) + (X) ⇒ X Translates to LEAX B,X IDX 1A E5 Pf PP 1 – – – – – – – – ABY (B) + (Y) ⇒ Y Translates to LEAY B,Y IDX 19 ED Pf PP 1 – – – – – – – – ADCA #opr8i ADCA opr8a ADCA opr16a ADCA oprx0_xysp ADCA oprx9,xysp ADCA oprx16,xysp ADCA [D,xysp] ADCA [oprx16,xysp] (A) + (M) + C ⇒ A Add with Carry to A IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] 89 ii 99 dd B9 hh ll A9 xb A9 xb ff A9 xb ee ff A9 xb A9 xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – ∆ – ∆ ∆ ∆ ∆ ADCB #opr8i ADCB opr8a ADCB opr16a ADCB oprx0_xysp ADCB oprx9,xysp ADCB oprx16,xysp ADCB [D,xysp] ADCB [oprx16,xysp] (B) + (M) + C ⇒ B Add with Carry to B IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] C9 ii D9 dd F9 hh ll E9 xb E9 xb ff E9 xb ee ff E9 xb E9 xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – ∆ – ∆ ∆ ∆ ∆ ADDA #opr8i ADDA opr8a ADDA opr16a ADDA oprx0_xysp ADDA oprx9,xysp ADDA oprx16,xysp ADDA [D,xysp] ADDA [oprx16,xysp] (A) + (M) ⇒ A Add without Carry to A IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] 8B ii 9B dd BB hh ll AB xb AB xb ff AB xb ee ff AB xb AB xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – ∆ – ∆ ∆ ∆ ∆ ADDB #opr8i ADDB opr8a ADDB opr16a ADDB oprx0_xysp ADDB oprx9,xysp ADDB oprx16,xysp ADDB [D,xysp] ADDB [oprx16,xysp] (B) + (M) ⇒ B Add without Carry to B IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] CB ii DB dd FB hh ll EB xb EB xb ff EB xb ee ff EB xb EB xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – ∆ – ∆ ∆ ∆ ∆ ADDD #opr16i ADDD opr8a ADDD opr16a ADDD oprx0_xysp ADDD oprx9,xysp ADDD oprx16,xysp ADDD [D,xysp] ADDD [oprx16,xysp] (A:B) + (M:M+1) ⇒ A:B Add 16-Bit to D (A:B) IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] C3 jj kk D3 dd F3 hh ll E3 xb E3 xb ff E3 xb ee ff E3 xb E3 xb ee ff PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP – – – – ∆ ∆ ∆ ∆ ANDA #opr8i ANDA opr8a ANDA opr16a ANDA oprx0_xysp ANDA oprx9,xysp ANDA oprx16,xysp ANDA [D,xysp] ANDA [oprx16,xysp] (A) • (M) ⇒ A Logical AND A with Memory IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] 84 ii 94 dd B4 hh ll A4 xb A4 xb ff A4 xb ee ff A4 xb A4 xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – – – ∆ ∆ 0 – ANDB #opr8i ANDB opr8a ANDB opr16a ANDB oprx0_xysp ANDB oprx9,xysp ANDB oprx16,xysp ANDB [D,xysp] ANDB [oprx16,xysp] (B) • (M) ⇒ B Logical AND B with Memory IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] C4 ii D4 dd F4 hh ll E4 xb E4 xb ff E4 xb ee ff E4 xb E4 xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – – – ∆ ∆ 0 – ANDCC #opr8i (CCR) • (M) ⇒ CCR Logical AND CCR with Memory IMM 10 ii PP ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. |
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