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HCS12 Datasheet(PDF) 382 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 382 Page - Freescale Semiconductor, Inc |
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382 / 452 page  S12CPUV2 Reference Manual, Rev. 4.0 382 Freescale Semiconductor ASL opr16a ASL oprx0_xysp ASL oprx9,xysp ASL oprx16,xysp ASL [D,xysp] ASL [oprx16,xysp] ASLA ASLB Arithmetic Shift Left Arithmetic Shift Left Accumulator A Arithmetic Shift Left Accumulator B EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH 78 hh ll 68 xb 68 xb ff 68 xb ee ff 68 xb 68 xb ee ff 48 58 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O rOPw rPw rPOw frPPw fIfrPw fIPrPw O O – – – – ∆ ∆ ∆ ∆ ASLD Arithmetic Shift Left Double INH 59 OO – – – – ∆ ∆ ∆ ∆ ASR opr16a ASR oprx0_xysp ASR oprx9,xysp ASR oprx16,xysp ASR [D,xysp] ASR [oprx16,xysp] ASRA ASRB Arithmetic Shift Right Arithmetic Shift Right Accumulator A Arithmetic Shift Right Accumulator B EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH 77 hh ll 67 xb 67 xb ff 67 xb ee ff 67 xb 67 xb ee ff 47 57 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O rOPw rPw rPOw frPPw fIfrPw fIPrPw O O – – – – ∆ ∆ ∆ ∆ BCC rel8 Branch if Carry Clear (if C = 0) REL 24 rr PPP/P 1 PPP/P 1 – – – – – – – – BCLR opr8a, msk8 BCLR opr16a, msk8 BCLR oprx0_xysp, msk8 BCLR oprx9,xysp, msk8 BCLR oprx16,xysp, msk8 (M) • (mm) ⇒ M Clear Bit(s) in Memory DIR EXT IDX IDX1 IDX2 4D dd mm 1D hh ll mm 0D xb mm 0D xb ff mm 0D xb ee ff mm rPwO rPwP rPwO rPwP frPwPO rPOw rPPw rPOw rPwP frPwOP – – – – ∆ ∆ 0 – BCS rel8 Branch if Carry Set (if C = 1) REL 25 rr PPP/P 1 PPP/P 1 – – – – – – – – BEQ rel8 Branch if Equal (if Z = 1) REL 27 rr PPP/P 1 PPP/P 1 – – – – – – – – BGE rel8 Branch if Greater Than or Equal (if N ⊕ V = 0) (signed) REL 2C rr PPP/P 1 PPP/P 1 – – – – – – – – BGND Place CPU in Background Mode see CPU12 Reference Manual INH 00 VfPPP VfPPP – – – – – – – – BGT rel8 Branch if Greater Than (if Z + (N ⊕ V) = 0) (signed) REL 2E rr PPP/P 1 PPP/P 1 – – – – – – – – BHI rel8 Branch if Higher (if C + Z = 0) (unsigned) REL 22 rr PPP/P 1 PPP/P 1 – – – – – – – – BHS rel8 Branch if Higher or Same (if C = 0) (unsigned) same function as BCC REL 24 rr PPP/P 1 PPP/P 1 – – – – – – – – BITA #opr8i BITA opr8a BITA opr16a BITA oprx0_xysp BITA oprx9,xysp BITA oprx16,xysp BITA [D,xysp] BITA [oprx16,xysp] (A) • (M) Logical AND A with Memory Does not change Accumulator or Memory IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] 85 ii 95 dd B5 hh ll A5 xb A5 xb ff A5 xb ee ff A5 xb A5 xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – – – ∆ ∆ 0 – BITB #opr8i BITB opr8a BITB opr16a BITB oprx0_xysp BITB oprx9,xysp BITB oprx16,xysp BITB [D,xysp] BITB [oprx16,xysp] (B) • (M) Logical AND B with Memory Does not change Accumulator or Memory IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] C5 ii D5 dd F5 hh ll E5 xb E5 xb ff E5 xb ee ff E5 xb E5 xb ee ff P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rfP rOP rfP rPO frPP fIfrfP fIPrfP – – – – ∆ ∆ 0 – BLE rel8 Branch if Less Than or Equal (if Z + (N ⊕ V) = 1) (signed) REL 2F rr PPP/P 1 PPP/P 1 – – – – – – – – BLO rel8 Branch if Lower (if C = 1) (unsigned) same function as BCS REL 25 rr PPP/P 1 PPP/P 1 – – – – – – – – Note 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken. Table A-1. Instruction Set Summary (Sheet 2 of 14) Source Form Operation Addr. Mode Machine Coding (hex) Access Detail S X H I N Z V C HCS12 M68HC12 C 0 b7 b0 C 0 b7 b0 AB b7 b0 C b7 b0 |
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