PIC12F519-ESLASHMS datasheet(25/96 Pages) MICROCHIP

25 / 96 page

DS41319B-page 23

PIC12F519

6.0

I/O PORT

As with any other register, the I/O register(s) can be

written and read under program control. However, read

instructions (e.g., MOVF PORTB,W) always read the I/O

pins independent of the pin’s Input/Output modes. On

Reset, all I/O ports are defined as input (inputs are at

high-impedance) since the I/O control registers are all

set.

6.1

GPIO

GPIO is an 8-bit I/O register. Only the low-order 6 bits

are used (GP<5:0>). Bits 7 and 6 are unimplemented

and read as ‘0’s. Please note that GP3 is an input-only

pin. The Configuration Word can set several I/O’s to

alternate functions. When acting as alternate functions,

the pins will read as ‘0’ during a port read. Pins GP0,

GP1, and GP3 can be configured with weak pull-ups

and also for wake-up on change. The wake-up on

change and weak pull-up functions are not pin select-

able. If GP3/MCLR is configured as MCLR, weak pull-

up is always on and wake-up on change for this pin is

not enabled.

6.2

TRIS Registers

The Output Driver Control registers are loaded with

the contents of the W Register by executing the TRIS

instruction. A ‘1’ from a TRISGPIO Register bit puts

the corresponding output driver in a high-impedance

(Input) mode. A ‘0’ puts the contents of the output data

latch on the selected pins, enabling the output buffer.

The TRISGPIO register is “write-only”. Bits <5:0> are

set (output drivers disabled) upon Reset.

TABLE 6-1:

WEAK PULL-UP ENABLED PINS

Note:

If the T0CS bit is set to ‘1’, it will override

the TRISGPIO function on the T0CKI pin.

WPU

GP0

GP1

GP2

GP3

Y(1)

GP4

GP5

GP6

Note 1:

When MCLRE = 1, the weak pull-up on GP3/MCLR is always

enabled.

WPU = Weak pull-up; WU = Wake-up.

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