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PIC12F519-E/MS Datasheet(PDF) 43 Page - Microchip Technology |
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PIC12F519-E/MS Datasheet(HTML) 43 Page - Microchip Technology |
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43 / 96 page ![]() © 2008 Microchip Technology Inc. DS41319B-page 41 PIC12F519 PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it. OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. For the PIC12F519 device, only bits <7:1> of OSCCAL are used for calibration. See Register 4-3 for more information. 8.3 Reset The device differentiates between various kinds of Reset: • Power-on Reset (POR) •MCLR Reset during normal operation •MCLR Reset during Sleep • WDT Time-out Reset during normal operation • WDT Time-out Reset during Sleep • Wake-up from Sleep on pin change Some registers are not reset in any way, and they are unknown on Power-on Reset (POR) and unchanged in any other Reset. Most other registers are reset to “Reset state” on Power-on Reset (POR), MCLR, WDT or Wake-up on pin change Reset during normal operation. They are not affected by a WDT Reset during Sleep or MCLR Reset during Sleep, since these Resets are viewed as resumption of normal operation. The exceptions to this are TO, PD and GPWUF bits. They are set or cleared differently in different Reset situations. These bits are used in software to determine the nature of Reset. See Table 8-3 for a full description of Reset states of all registers. TABLE 8-3: RESET CONDITIONS FOR REGISTERS Note: Erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. Note: The bit 0 of the OSCCAL register is unimplemented and should be written as ‘0’ when modifying OSCCAL for compatibility with future devices. Register Address Power-on Reset MCLR Reset, WDT Time-out, Wake-up On Pin Change W— qqqq qqq0(1) qqqq qqq0(1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 0-01 1xxx q-0q quuu(2), (3) FSR 04h 110x xxxx 11uu uuuu OSCCAL 05h 1111 111- uuuu uuu- PORTB 06h --xx xxxx --uu uuuu OPTION — 1111 1111 1111 1111 TRIS — --11 1111 --11 1111 EECON 21h ---0 x000 ---0 q000 EEDATA 25h xxxx xxxx uuuu uuuu EEADR 26h --xx xxxx --uu uuuu Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: Bits <7:1> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. 2: See Table 8-4 for Reset value for specific conditions. 3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. |
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