PIC12F519-ESLASHMS datasheet(40/96 Pages) MICROCHIP

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PIC12F519

DS41319B-page 38

CONFIG: CONFIGURATION WORD REGISTER(1)

—CPDF

IOSCFS

MCLRE

WDTE

FOSC1

FOSC0

bit 7

bit 0

bit 7

Unimplemented

: Read as ‘1’

bit 6

CPDF:

Code Protection bit - Flash Data Memory

= Code protection off

= Code protection on

bit 5

IOSCFS:

Internal Oscillator Frequency Select bit

= 8 MHz INTOSC frequency

= 4 MHz INTOSC frequency

bit 4

MCLRE:

Master Clear Enable bit

= GP3/MCLR pin functions as MCLR

= GP3/MCLR pin functions as GP3, MCLR internally tied to VDD

bit 3

CP:

Code Protection bit - User Program Memory

= Code protection off

= Code protection on

bit 2

WDTE:

Watchdog Timer Enable bit

= WDT enabled

= WDT disabled

bit 1-0

FOSC<1:0>:

Oscillator Selection bits

= LP oscillator with 18 ms DRT(2)

= XT oscillator with 18 ms DRT(2)

= INTOSC with 1 ms DRT(2)

= EXTRC with 1 ms DRT(2)

Note 1:

Refer to the “PIC12F519 Memory Programming Specification”, DS41316 to determine how to

program/erase the Configuration Word.

DRT length (18 ms or 1 ms) is a function of clock mode selection. It is the responsibility of the application

designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in

acceptable operation. Refer to Figure 11-1 and Table 11-2 for VDD rise time and stability requirements for

this mode of operation.

PIC12F519-E/MS Datasheet(PDF) 40 Page - Microchip Technology

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