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PIC12F519-E/MS Datasheet(PDF) 27 Page - Microchip Technology |
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PIC12F519-E/MS Datasheet(HTML) 27 Page - Microchip Technology |
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27 / 96 page ![]() © 2008 Microchip Technology Inc. DS41319B-page 25 PIC12F519 6.3 I/O Interfacing The equivalent circuit for an I/O port pin is shown in Figure 6-1. All port pins, except GP3 which is input only, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF GPIO, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRISGPIO must be cleared (= 0). For use as an input, the corresponding TRISGPIO bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output. FIGURE 6-1: PIC12F519 EQUIVALENT CIRCUIT FOR I/O PINS – GP0/GP1 VDD VDD I/O Pin VSS Pin Change Q D Wake-up on change Latch Q D Q Q D CK Q Data Latch TRIS Latch RD Port TRIS ‘F’ WREG WR Data GPPU CK CK GP0/ICSPDAT GP1/ICSPCLK • General purpose I/O • General purpose I/O • In-Circuit Serial Programming™ data • In-circuit Serial Programming™ clock • Wake-up on input change trigger • Wake-up on input change trigger |
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