PIC12F519-ESLASHMS datasheet(36/96 Pages) MICROCHIP

36 / 96 page

PIC12F519

DS41319B-page 34

7.2

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer (WDT), respectively (see Section 8.6 “Watch-

dog Timer (WDT)”

). For simplicity, this counter is

being referred to as “prescaler” throughout this data

sheet.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF TMR0,

MOVWF TMR0,

etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the WDT. The prescaler is neither

readable nor writable. On a Reset, the prescaler con-

tains all ‘0’s.

7.2.1

SWITCHING PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software

control (i.e., it can be changed “on-the-fly” during pro-

gram execution). To avoid an unintended device Reset,

the following instruction sequence (Example 7-1) must

be executed when changing the prescaler assignment

from Timer0 to the WDT.

EXAMPLE 7-1:

CHANGING PRESCALER

(TIMER0

→ WDT)

To change the prescaler from the WDT to the Timer0

module, use the sequence shown in Example 7-2. This

sequence must be used even if the WDT is disabled. A

CLRWDT

instruction should be executed before

switching the prescaler.

EXAMPLE 7-2:

CHANGING PRESCALER

(WDT

→ TIMER0)

Note:

The prescaler may be used by either the

Timer0 module or the WDT, but not both.

Thus, a prescaler assignment for the

Timer0 module means that there is no

prescaler for the WDT and vice versa.

CLRWDT

;Clear WDT

CLRF

TMR0

;Clear TMR0 and Prescaler

MOVLW

b‘00xx1111’

OPTION

CLRWDT

;PS<2:0> are 000 or 001

MOVLW

b‘00xx1xxx’ ;Set Postscaler to

OPTION

;desired WDT rate

CLRWDT

;Clear WDT and

;prescaler

MOVLW

b‘xxxx0xxx’ ;Select TMR0, new

;prescale value and

;clock source

OPTION

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