HT82K70E-L datasheet(16/59 Pages) HOLTEK

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HT82K70E-L/HT82K70A-L/HT82K76E-L

Rev. 1.20

February 1, 2011

Output Pin Slew Rate Control

The output pin slew rate can be setup using a configura-

tion option and can be set to be either 0ns, 50ns, 100ns

or 200ns.

I/O Pin Structures

The accompanying diagrams illustrate the internal

structures of some I/O pin types. As the exact logical

construction of the I/O pin will differ from these draw-

ings, they are supplied as a guide only to assist with the

functional understanding of the I/O pins. The wide range

of pin-shared structures does not permit all types to be

shown.

Programming Considerations

Within the user program, one of the first things to con-

sider is port initialisation. After a reset, all of the data and

port control register will be set high. This means that all

I/O pins will default to an input state, the level of which

depends on the other connected circuitry and whether

pull-high options have been selected. If the PAC, PBC,

PCC, PDC, PEC and PFC.0~PFC.2 port control regis-

ter, are then programmed to setup some pins as out-

puts, these output pins will have an initial high output

value unless the associated PA, PB, PC, PD, PE and

PF0~PF2 port data registers are first programmed. Se-

lecting which pins are inputs and which are outputs can

be achieved byte-wide by loading the correct value into

the port control register or by programming individual

bits in the port control register using the

²SET [m].i² and

²CLR [m].i² instructions. Note that when using these bit

control instructions, a read-modify-write operation takes

place. The microcontroller must first read in the data on

the entire port, modify it to the required new bit values

and then rewrite this data back to the output ports.

All I/O pins has the additional capability of providing

wake-up functions. When the device is in the Power

Down Mode, various methods are available to wake the

device up. One of these is a high to low or low to high

transition of any of all I/O pins. Single or multiple pins on

all I/O pins can be setup to have this function.

Timer/Event Counters

The provision of timers form an important part of any

microcontroller, giving the designer a means of carrying

out time related functions. This device contains two

count-up timers of 16-bit capacities. As each timer has

three different operating modes, they can be configured

to operate as a general timer, an external event counter

or as a pulse width measurement device.

There are two types of registers related to the

Timer/Event Counters. The first is the register that con-

tain the actual value of the Timer/Event Counter and into

which an initial value can be preloaded, and is known as

TMR0H/TMR0L, TMR1H/TMR1L. Reading from this

ter. The second type of associated register is the Timer

Control Register, which defines the timer options and

determines how the Timer/Event Counter is to be used,

and has the name TMR0C or TMR1C. This device can

have the timer clocks configured to come from the inter-

nal clock sources. In addition, the timer clock sources

can also be configured to come from the external timer

pins.

The external clock source is used when the Timer/Event

Counter is in the event counting mode, the clock source

being provided on the external timer pin. The external

timer pin has the name TMR0 or TMR1. Depending

upon the condition of the T0E or T1E bit in the Timer

Control Register, each high to low, or low to high transi-

tion on the external timer input pin will increment the

Timer/Event Counter by one.

Configuring the Timer/Event Counter Input Clock

Source

The Timer/Event Counter

¢s clock can originate from vari-

ous sources. The instruction clock source or WDTOSC

(system clock source divided by 4) is used when the

Timer/Event Counter 0 or Timer/Event Counter 1 is in the

timer mode or in the pulse width measurement mode.

The external clock source is used when the Timer/Event

Counter is in the event counting mode, the clock source

being provided on the external timer pin, TMR0 or TMR1.

Depending upon the condition of the T0E or T1E bit, each

high to low, or low to high transition on the external timer

pin will increment the counter by one.

Timer Registers

- TMR0H/TMR0L, TMR1H/TMR1L

The timer registers are special function registers located

in the Special Purpose RAM Data Memory and are the

places where the actual timer values are stored. The

timer registers are known as TMR0L/ TMR0H, TMR1L

/TMR1H. The value in the timer registers increases by

one each time an internal clock pulse is received or an

external transition occurs on the external timer pin. The

timer will count from the initial value loaded by the

preload register to the full count of FFFFH for the 16-bit

timer at which point the timer overflows and an internal

interrupt signal is generated. The timer value will then

be reset with the initial preload register value and con-

tinue counting.

To achieve a maximum full range count of FFFFH, the

preload registers must first be cleared to all zeros. It

should be noted that after power-on, the preload register

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

W r i t e t o P o r t

R e a d f r o m P o r t

S y s t e m C l o c k

P o r t D a t a

Read/Write Timing

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